Datasheet AD7273, AD7274 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 3 MSPS 12-Bit A/D Converter in TSOT and MSOP Packages |
| 页数 / 页 | 28 / 7 — AD7273/AD7274. TIMING SPECIFICATIONS. Table 4. Limit at TMIN, TMAX. … |
| 文件格式/大小 | PDF / 410 Kb |
| 文件语言 | 英语 |
AD7273/AD7274. TIMING SPECIFICATIONS. Table 4. Limit at TMIN, TMAX. Parameter. AD7273/AD7274 Unit. Description. SCLK. VIH. SDATA. 1.4V. VIL
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AD7273/AD7274 TIMING SPECIFICATIONS
VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 4. Limit at TMIN, TMAX Parameter AD7273/AD7274 Unit Description
f 2 SCLK 500 kHz min3 48 MHz max tCONVERT 14 × tSCLK AD7274 12 × tSCLK AD7273 tQUIET 4 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 3 ns min Minimum CS pulse width t2 6 ns min CS to SCLK setup time t 4 3 4 ns max Delay from CS until SDATA three-state disabled t 4 4 15 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t 4 7 5 ns min SCLK to data valid hold time t8 14 ns max SCLK falling edge to SDATA three-state 5 ns min SCLK falling edge to SDATA three-state t9 4.2 ns max CS rising edge to SDATA three-state t 5 POWER-UP 1 μs max Power-up time from full power-down 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 The time required for the output to cross the VIH or VIL voltage. 5 See the Power-Up Times section
t4 t8 SCLK SCLK VIH SDATA 1.4V SDATA VIL
04973-002 04973-004 Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State
t7 SCLK VIH SDATA VIL
04973-003 Figure 3. Hold Time After SCLK Falling Edge Rev. 0 | Page 7 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AD7274 SPECIFICATIONS AD7273 SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7273/AD7274 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7273/AD7274 TIMING SPECIFICATIONS
VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted.1 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 4. Limit at TMIN, TMAX Parameter AD7273/AD7274 Unit Description
f 2 SCLK 500 kHz min3 48 MHz max tCONVERT 14 × tSCLK AD7274 12 × tSCLK AD7273 tQUIET 4 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 3 ns min Minimum CS pulse width t2 6 ns min CS to SCLK setup time t 4 3 4 ns max Delay from CS until SDATA three-state disabled t 4 4 15 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t 4 7 5 ns min SCLK to data valid hold time t8 14 ns max SCLK falling edge to SDATA three-state 5 ns min SCLK falling edge to SDATA three-state t9 4.2 ns max CS rising edge to SDATA three-state t 5 POWER-UP 1 μs max Power-up time from full power-down 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 The time required for the output to cross the VIH or VIL voltage. 5 See the Power-Up Times section
t4 t8 SCLK SCLK VIH SDATA 1.4V SDATA VIL
04973-002 04973-004 Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State
t7 SCLK VIH SDATA VIL
04973-003 Figure 3. Hold Time After SCLK Falling Edge Rev. 0 | Page 7 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AD7274 SPECIFICATIONS AD7273 SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7273/AD7274 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE