Datasheet AD7760 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 2.5 MSPS, 24-Bit, 100 dB Sigma-Delta ADC with On-Chip Buffer |
| 页数 / 页 | 37 / 7 — TIMING SPECIFICATIONS. Table 3. Parameter. Limit at TMIN, TMAX. Unit. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 866 Kb |
| 文件语言 | 英语 |
TIMING SPECIFICATIONS. Table 3. Parameter. Limit at TMIN, TMAX. Unit. Description
该数据表的模型线
文件文字版本
AD7760
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1, 2 1 0.5 × tICLK typ DRDY pulse width t2 10 ns min DRDY falling edge to CS falling edge t3 3 ns min RD/WR setup time to CS falling edge t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t6 tICLK min CS high pulse width between reads t7 3 ns min RD/WR hold time to CS rising edge t8 11 ns max Bus relinquish time t 2 9 0.5 × tICLK typ DRDY high period t 2 10 0.5 × tICLK typ DRDY low period t11 (0.5 × tICLK) + 16 ns max Data access time t 3, 4 12 23 ns min Data valid prior to DRDY rising edge t 3, 4 13 19 ns min Data valid after DRDY rising edge t14 11 ns max Bus relinquish time t15 4 × tICLK min CS low write pulse width t16 4 × tICLK min CS high period between address and data t17 5 ns min Data setup time t18 0 ns min Data hold time t 4, 5 19 23 ns min Data valid prior to MCLK falling edge while DRDY is logic low t 4, 5 20 19 ns min Data valid after MCLK falling edge while DRDY is logic low 1 tICLK = 1/fICLK. 2 When ICLK = MCLK, DRDY pulse width depends on the mark-space ratio of applied MCLK. 3 Valid when using the modulator output mode with CDIV = 1. 4 See the Modulator Data Output Mode section for timing diagrams. 5 Valid when using the modulator output mode with CDIV = 0. Rev. A | Page 6 of 36
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3. Parameter Limit at TMIN, TMAX Unit Description
fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t 1, 2 1 0.5 × tICLK typ DRDY pulse width t2 10 ns min DRDY falling edge to CS falling edge t3 3 ns min RD/WR setup time to CS falling edge t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t6 tICLK min CS high pulse width between reads t7 3 ns min RD/WR hold time to CS rising edge t8 11 ns max Bus relinquish time t 2 9 0.5 × tICLK typ DRDY high period t 2 10 0.5 × tICLK typ DRDY low period t11 (0.5 × tICLK) + 16 ns max Data access time t 3, 4 12 23 ns min Data valid prior to DRDY rising edge t 3, 4 13 19 ns min Data valid after DRDY rising edge t14 11 ns max Bus relinquish time t15 4 × tICLK min CS low write pulse width t16 4 × tICLK min CS high period between address and data t17 5 ns min Data setup time t18 0 ns min Data hold time t 4, 5 19 23 ns min Data valid prior to MCLK falling edge while DRDY is logic low t 4, 5 20 19 ns min Data valid after MCLK falling edge while DRDY is logic low 1 tICLK = 1/fICLK. 2 When ICLK = MCLK, DRDY pulse width depends on the mark-space ratio of applied MCLK. 3 Valid when using the modulator output mode with CDIV = 1. 4 See the Modulator Data Output Mode section for timing diagrams. 5 Valid when using the modulator output mode with CDIV = 0. Rev. A | Page 6 of 36