Datasheet AD7623 (Analog Devices) - 9

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AD7623 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS F U EF B R FBUFIN DD FGND F PD PD RE TEMP AV IN+ AGND AGND NC IN– RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7623 DGND 6 31 RD TOP VIEW DGND 7 30 (Not to Scale) DGND SER/PAR 8 29 BUSY D0 9 28 D15 D1 10 27 D14 11 D2/DIVSCLK[0] 26 D13 D3/DIVSCLK[1] 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 NC = NO CONNECT C IN C D DD CLK DGND DOUT RROR VSYN OGND OVDD DV /S /S 10/SYN /IN D9 D D4/EXT/INT 5 /RDC/S D8 /RDE D D6/INVSCLK 1 D7 D1
05574-004 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 41, 42 AGND P Analog Power Ground Pin. 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 40 NC No Connect. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6, 7 DGND P Digital Power Ground. 8 SER/PAR DI Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low, the parallel port is selected. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. 11, 12 D[2:3] DI/O When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. or When SER/PAR = high, serial clock division selection. When using serial master read after convert DIVSCLK[0:1] mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 DI/O When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. or EXT/INT When SER/PAR = high, serial clock source select. This input is used to select the internally generated (master ) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. 14 D5 DI/O When SER/PAR = low, this output is used as Bit 5 of the parallel port data output bus. or INVSYNC When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. 15 D6 DI/O When SER/PAR = low, this output is used as Bit 6 of the parallel port data output bus. or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal. Rev. 0 | Page 8 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS SERIAL CLOCK TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE Single-to-Differential Driver VOLTAGE REFERENCE INPUT Internal Reference (PDBUF = Low, PDREF = Low) External 1.2 V Reference and Internal Buffer (PDREF = High, PBBUF = Low) External Reference (PDBUF = High, PRBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLY Power Sequencing Power-Up POWER DISSIPATION VS. THROUGHPUT CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Previous Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION LAYOUT EVALUATING THE AD7623 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE