Datasheet AD7276, AD7277, AD7278 (Analog Devices)

3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT Data Sheet AD7276/ AD7277/ AD7278 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput rate: 3 MSPS VDD Specified for V of 2.35 V to 3.6 V DD Power consumption 12.6 mW at 3 MSPS with 3 V supplies 12-/10-/8-BIT Wide input bandwidth SUCCESSIVE VIN T/H APPROXIMATION 70 dB SNR at 1 MHz input frequency ADC Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI-/QSPI™-/MICROWIRE™-/DSP compatible SCLK Temperature range: −40°C to +125°C AD7276/ CONTROL SDATA Power-down mode: 0.1 µA typical AD7277/ LOGIC AD7278 CS 6-lead TSOT package 8-lead MSOP package
001
AD7476 a nd AD7476A pi n compatible GND
04903-
GENERAL DESCRIPTION
Figure 1. The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed,
Table 1.
low power, successive approximation analog-to-digital converters
Part Number Resolution Package
(ADCs), respectively. The parts operate from a single 2.35 V AD7276 12 8-Lead MSOP 6-Lead TSOT to 3.6 V power supply and feature throughput rates of up to AD7277 10 8-Lead MSOP 6-Lead TSOT 3 MSPS. The parts contain a low noise, wide bandwidth track- AD7278 8 8-Lead MSOP 6-Lead TSOT and-hold amplifier that can handle input frequencies in excess AD72741 12 8-Lead MSOP 8-Lead TSOT of 55 MHz. AD72731 10 8-Lead MSOP 8-Lead TSOT The conversion process and data acquisition are controlled 1 Part contains external reference pin. using CS and the serial clock, al owing the devices to interface with microprocessors or DSPs. The input signal is sampled on
PRODUCT HIGHLIGHTS
the fal ing edge of CS, and the conversion is initiated at this 1. 3 MSPS ADCs in a 6-lead TSOT package. point. There are no pipeline delays associated with the part. 2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/ The AD7276/AD7277/AD7278 use advanced design techniques AD7478A pin compatible. to achieve very low power dissipation at high throughput rates. 3. High throughput with low power consumption. 4. Flexible power/serial clock speed management. This al ows The reference for the part is taken internal y from VDD. This maximum power efficiency at low throughput rates. al ows the widest dynamic input range to the ADC; therefore, 5. Reference derived from the power supply. the analog input range for the part is 0 to VDD. The conversion 6. No pipeline delay. The parts feature a standard successive rate is determined by the SCLK. approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
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Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7276 SPECIFICATIONS AD7277 SPECIFICATIONS AD7278 SPECIFICATIONS TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM Analog Input Digital Inputs MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode Power-Up Times POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278 to Blackfin Processor APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES