Datasheet AD7942 (Analog Devices) - 7

制造商Analog Devices
描述14-Bit, 250 kSPS PulSAR , Pseudo Differential ADC in MSOP/LFCSP
页数 / 页25 / 7 — AD7942. Data Sheet. Table 4. Parameter. Symbol Min. Typ. Max. Unit. …
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AD7942. Data Sheet. Table 4. Parameter. Symbol Min. Typ. Max. Unit. Timing Diagrams. 500µA. IOL. TO SDO. 1.4V. 50pF. 70% VIO. 30% VIO. tDELAY

AD7942 Data Sheet Table 4 Parameter Symbol Min Typ Max Unit Timing Diagrams 500µA IOL TO SDO 1.4V 50pF 70% VIO 30% VIO tDELAY

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AD7942 Data Sheet
VDD = 2.3 V to 4.5 V1, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO ≥ 3 V 29 ns VIO ≥ 2.7 V 35 ns VIO ≥ 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO ≥ 3 V 24 ns VIO ≥ 2.7 V 30 ns VIO ≥ 2.3 V 35 ns CNV or SDI Low to SDO D13 MSB Valid (CS Mode) tEN VIO ≥ 2.7 V 18 ns VIO ≥ 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 ns 1 See Figure 2 and Figure 3 for load conditions.
Timing Diagrams 500µA IOL TO SDO 1.4V CL 50pF
02
500µA I
0
OH
7- 465 0 Figure 2. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 NOTES
03
1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0 7-
2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
65 04 Figure 3. Voltage Reference Levels for Timing Rev. C | Page 6 of 24 Document Outline Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface /CS Mode 3-Wire Without Busy Indicator /CS Mode 3-Wire with Busy Indicator /CS Mode 4-Wire Without Busy Indicator /CS Mode 4-Wire with Busy Indicator Chain Mode Without Busy Indicator Chain Mode with Busy Indicator Application Hints Layout Evaluating the Performance of AD7942 Outline Dimensions Ordering Guide