Datasheet AD7686 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 500 kSPS 16-BIT PulSAR® A/D Converter in MSOP/QFN |
| 页数 / 页 | 29 / 6 — Data Sheet. AD7686. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 573 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7686. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. Min. Typ. Max. Unit. 70% VIO. 500µA. IOL. 30% VIO. tDELAY. TO SDO. 1.4V
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Data Sheet AD7686 TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 1.6 µs Acquisition Time tACQ 400 ns Time Between Conversions tCYC 2 µs CNV Pulse Width ( CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns
70% VIO 500µA IOL 30% VIO tDELAY tDELAY TO SDO 1.4V 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 C 0.8V OR 0.5V2 0.8V OR 0.5V2 L 50pF 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2
003
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
004
500µA IOH
02969- 02969- Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. C | Page 5 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface CS/ MODE 3-Wire, No Busy Indicator CS/ Mode 3-Wire with Busy Indicator CS/ Mode 4-Wire, No Busy Indicator CS/ Mode 4-Wire with Busy Indicator Chain Mode, No Busy Indicator Chain Mode with Busy Indicator Application Hints Layout Evaluating the Performance of the AD7686 True 16-Bit Isolated Application Example Outline Dimensions Ordering Guide
Data Sheet AD7686 TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 1.6 µs Acquisition Time tACQ 400 ns Time Between Conversions tCYC 2 µs CNV Pulse Width ( CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns VIO Above 2.3 V 20 ns SCK Low Time tSCKL 7 ns SCK High Time tSCKH 7 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 14 ns VIO Above 3 V 15 ns VIO Above 2.7 V 16 ns VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 4.5 V 15 ns VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 15 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 3 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI VIO Above 4.5 V 15 ns VIO Above 2.3 V 26 ns
70% VIO 500µA IOL 30% VIO tDELAY tDELAY TO SDO 1.4V 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 C 0.8V OR 0.5V2 0.8V OR 0.5V2 L 50pF 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2
003
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
004
500µA IOH
02969- 02969- Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. C | Page 5 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface CS/ MODE 3-Wire, No Busy Indicator CS/ Mode 3-Wire with Busy Indicator CS/ Mode 4-Wire, No Busy Indicator CS/ Mode 4-Wire with Busy Indicator Chain Mode, No Busy Indicator Chain Mode with Busy Indicator Application Hints Layout Evaluating the Performance of the AD7686 True 16-Bit Isolated Application Example Outline Dimensions Ordering Guide