Datasheet AD7266 (Analog Devices) - 9

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AD7266 Pin No. Mnemonic Description
28, 30 DOUTB, Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the DOUTA falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. See the Serial Interfac sec e tion. 31 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different than that at AVDD and DVDD but should never exceed either by more than 0.3 V. 32 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND. EPAD Exposed Pad. The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground. Rev. B | Page 8 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION OUTPUT CODING TRANSFER FUNCTIONS DIGITAL INPUTS VDRIVE MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7266 TO ADSP-218x AD7266 TO ADSP-BF53x AD7266 TO TMS320C541 AD7266 TO DSP563xx APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP EVALUATING THE AD7266 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE