Datasheet AD7265 (Analog Devices) - 5

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AD7265 Data Sheet Parameter Specification Unit Test Conditions/Comments
DC Leakage Current ±1 µA max Input Capacitance 45 pF typ When in track 10 pF typ When in hold REFERENCE INPUT/OUTPUT Reference Output Voltage 8 2.5 V min/V max ±0.2% max @ 25°C Long-Term Stability 150 ppm typ For 1000 hours Output Voltage Hysteresis2 50 ppm typ Reference Input Voltage Range 0.1/VDD V min/V max See Typical Performance Characteristics section DC Leakage Current ±2 µA max External reference applied to Pin DCAPA/Pin DCAPB Input Capacitance 25 pF typ DCAPA, DCAPB Output Impedance 10 Ω typ Reference Temperature Coefficient 20 ppm/°C max 10 ppm/°C typ VREF Noise 20 µV rms typ LOGIC INPUTS Input High Voltage, VINH 2.8 V min Input Low Voltage, VINL 0.4 V max Input Current, IIN ±15 nA typ VIN = 0 V or VDRIVE Input Capacitance, C 3 IN 5 pF typ LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V min Output Low Voltage, VOL 0.4 V max Floating State Leakage Current ±1 µA max Floating State Output Capacitance3 7 pF typ Output Coding Straight (natural) binary SGL/DIFF = 1 with 0 V to VREF range selected Twos complement SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range CONVERSION RATE Conversion Time 14 SCLK cycles 875 ns with SCLK = 16 MHz Track-and-Hold Acquisition Time3 90 ns max Full-scale step input; VDD = 5 V 110 ns max Full-scale step input; VDD = 3 V Throughput Rate 1 MSPS max POWER REQUIREMENTS VDD 2.7/5.25 V min/V max VDRIVE 2.7/5.25 V min/V max I DD Digital I/Ps = 0 V or VDRIVE Normal Mode (Static) 2.3 mA max VDD = 5.25 V Operational, fS = 1 MSPS 4 mA max VDD = 5.25 V; 3.5 mA typ fS = 1 MSPS 3.2 mA max VDD = 3.6 V; 2.7 mA typ Partial Power-Down Mode 500 µA max Static Full Power-Down Mode (VDD) 1 µA max TA = −40°C to +85°C 2.8 µA max TA > 85°C to 125°C Power Dissipation Normal Mode (Operational) 21 mW max VDD = 5.25 V Partial Power-Down (Static) 2.625 mW max VDD = 5.25 V Full Power-Down (Static) 5.25 µW max VDD = 5.25 V, TA = −40°C to +85°C 1 Temperature range is −40°C to +125°C. 2 See Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Guaranteed no missed codes to 12 bits. 5 VIN− or VIN+ must remain within GND/VDD. 6 VIN− = 0 V for specified performance. For ful input range on VIN− pin, see Figure 28 and Figure 29. 7 For ful common-mode range, see Figure 24 and Figure 25. 8 Relates to Pin DCAPA or Pin DCAPB. Rev. B | Page 4 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION OUTPUT CODING TRANSFER FUNCTIONS DIGITAL INPUTS VDRIVE MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7265 TO ADSP-218x AD7265 to ADSP-BF53x AD7265 TO TMS320C541 AD7265 TO DSP563xx APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP EVALUATING THE AD7265 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE