Datasheet AD7265 (Analog Devices) - 8

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Data Sheet AD7265 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS E A B E A B V K V K DD UT ND UT DD UT ND UT DRI O O CL DRI O O CL DV V D DG D S CS A0 DV V D DG D S CS A0 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25 DGND 1 24 DGND 1 24 A1 A1 PIN 1 REF SELECT 2 23 A2 REF SELECT 2 23 A2 AV 3 22 SGL/DIFF DD AD7265 AV 3 22 SGL/DIFF DD D 4 21 RANGE CAPA AD7265 TOP VIEW D 4 21 RANGE AGND 5 20 D CAPA CAPB TOP VIEW (Not to Scale) AGND 6 19 AGND AGND 5 (Not to Scale) 20 DCAPB V 7 18 V A1 B1 AGND 6 19 AGND V 8 17 V A2 B2 V 7 A1 18 VB1 9 1 V 8 17 V 10 1 12 13 14 15 16 A2 B2
002
A3 A4 A5 A6 B6 B5 B4 B3 9 10 11 12 13 14 15 16 V V V V V V V V
04674- 041
A3 A4 A5 A6 B6 B5 B4 B3 NOTES V V V V V V V V
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1. EXPOSED PAD. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE PACK CONNECT THE EPAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS
Figure 2. 32-Lead CP-32-7 Figure 3. 32-Lead SU-32-2
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 29 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 2 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265 through the DCAPA pin and/or the DCAPB pin. 3 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND. 4, 20 DCAPA, DCAPB Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. The range of the external reference is dependent on the analog input range selected. 5, 6, 19 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7 to 12 VA1 to VA6 Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 6. 13 to 18 VB6 to VB1 Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 6. 21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic high when CS goes low, the analog input range is 2 × VREF. See the Analog Input Selection section for details. 22 SGL/DIFF Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input Selection section for details. 23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for multiplexer address decoding. 26 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265 and framing the serial data transfer. Rev. B | Page 7 of 28 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION OUTPUT CODING TRANSFER FUNCTIONS DIGITAL INPUTS VDRIVE MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7265 TO ADSP-218x AD7265 to ADSP-BF53x AD7265 TO TMS320C541 AD7265 TO DSP563xx APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP EVALUATING THE AD7265 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE