Datasheet AD7933, AD7934 (Analog Devices) - 7

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AD7933/AD7934 TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to TMAX, unless otherwise noted.
Table 4. Limit at TMIN, TMAX Parameter
1
AD7933 AD7934 Unit Description
f 2 CLKIN 700 700 kHz min CLKIN frequency 25.5 25.5 MHz max tQUIET 30 30 ns min Minimum time between end of read and start of next conversion, that is, the time from when the data bus goes into three-state until the next falling edge of CONVST t1 10 10 ns min CONVST pulse width t2 15 15 ns min CONVST falling edge to CLKIN falling edge setup time t3 50 50 ns max CLKIN falling edge to BUSY rising edge t4 0 0 ns min CS to WR setup time t5 0 0 ns min CS to WR hold time t6 10 10 ns min WR pulse width t7 10 10 ns min Data setup time before WR t8 10 10 ns min Data hold after WR t9 10 10 ns min New data valid before falling edge of BUSY t10 0 0 ns min CS to RD setup time t11 0 0 ns min CS to RD hold time t12 30 30 ns min RD pulse width t 3 13 30 30 ns max Data access time after RD t 4 14 3 3 ns min Bus relinquish time after RD 50 50 ns max Bus relinquish time after RD t15 0 0 ns min HBEN to RD setup time t16 0 0 ns min HBEN to RD hold time t17 10 10 ns min Minimum time between reads/writes t18 0 0 ns min HBEN to WR setup time t19 10 10 ns min HBEN to WR hold time t20 40 40 ns max CLKIN falling edge to BUSY falling edge t21 15.7 15.7 ns min CLKIN low pulse width t22 7.8 7.8 ns min CLKIN high pulse width 1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications are with a 25 pF load capacitance (see Figure 34, Figure 35, Figure 36, and Figure 37). 2 Minimum CLKIN for specified performance; with slower SCLK frequencies, performance specifications apply typically. 3 The time required for the output to cross 0.4 V or 2.4 V. 4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Rev. B | Page 7 of 32 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7933 SPECIFICATIONS AD7934 SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CONTROL REGISTER SEQUENCER OPERATION Writing to the Control Register to Program the Sequencer CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT STRUCTURE ANALOG INPUTS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION Traditional Multichannel Operation (SEQ0 = SEQ1 = 0) Using the Sequencer: Consecutive Sequence (SEQ0 = 1, SEQ1 = 1) REFERENCE Digital Inputs VDRIVE Input PARALLEL INTERFACE Reading Data from the AD7933/AD7934 Writing Data to the AD7933/AD7934 POWER MODES OF OPERATION Normal Mode (PM1 = PM0 = 0) Autoshutdown (PM1 = 0; PM0 = 1) Autostandby (PM1 = 1; PM0 = 0) Full Shutdown Mode (PM1 = 1; PM0 = 1) POWER vs. THROUGHPUT RATE MICROPROCESSOR INTERFACING AD7933/AD7934 to ADSP-21xx Interface AD7933/AD7934 to ADSP-21065L Interface AD7933/AD7934 to TMS32020, TMS320C25, and TMS320C5x Interface AD7933/AD7934 to 80C186 Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7933/AD7934 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE