Datasheet AD9481 (Analog Devices) - 10

制造商Analog Devices
描述8-Bit, 250 MSPS, 3.3 V A/D Converter
页数 / 页29 / 10 — AD9481. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. AGND. VIN. 44 43 42. …
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文件语言英语

AD9481. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. AGND. VIN. 44 43 42. 40 39 38. CLK+ 1. SENSE. CLK–. PIN 1. AVDD. DRVDD. PDWN. TOP VIEW. DRGND

AD9481 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND VIN 44 43 42 40 39 38 CLK+ 1 SENSE CLK– PIN 1 AVDD DRVDD PDWN TOP VIEW DRGND

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文件文字版本

AD9481 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS + DD + DD EF DS DS S3 AV AGND VIN VIN AGND AV AGND VR 44 43 42 41 40 39 38 37 36 35 34 CLK+ 1 33 SENSE CLK– 2 PIN 1 32 AGND AVDD 3 31 AVDD AGND 4 30 AVDD AD9481 DRVDD 5 29 PDWN TOP VIEW DRGND 6 (Not to Scale) 28 S1 D7A (MSB) 7 27 DRGND D6A 8 26 D7B (MSB) D5A 9 25 D6B D4A 10 24 D5B D3A 11 23 D4B 12 13 14 15 16 17 18 19 20 21 22 A A ) ) B B B B DD B D2 D1 D1 D2 D3 DCO– DCO+ A (LS DRGND DRV B (LS
05045-003
D0 D0
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions Pin Pin No. Name Description No. Name Description
1 CLK+ Input Clock—True 25 D6B Data Output Bit 6—Channel B 2 CLK− Input Clock—Complement 26 D7B Data Output Bit 7—Channel B (MSB) 3 AVDD 3.3 V Analog Supply 27 DRGND Digital Ground 4 AGND Analog Ground 28 S1 Data Format Select and Duty Cycle Stabilizer 5 DRVDD 3.3 V Digital Output Supply Select 6 DRGND Digital Ground 29 PDWN Power-Down Selection 7 D7A Data Output Bit 7—Channel A (MSB) 30 AVDD 3.3 V Analog Supply 8 D6A Data Output Bit 6—Channel A 31 AVDD 3.3 V Analog Supply 9 D5A Data Output Bit 5—Channel A 32 AGND Analog Ground 10 D4A Data Output Bit 4—Channel A 33 SENSE Reference Mode Selection 11 D3A Data Output Bit 3—Channel A 34 VREF Voltage Reference Input/Output 12 D2A Data Output Bit 2—Channel A 35 AGND Analog Ground 13 D1A Data Output Bit 1—Channel A 36 AVDD 3.3 V Analog Supply 14 D0A Data Output Bit 0—Channel A (LSB) 37 AGND Analog Ground 15 DRGND Digital Ground 38 VIN− Analog Input—Complement 16 DCO− Data Clock Output—Complement 39 VIN+ Analog Input—True 17 DCO+ Data Clock Output—True 40 AGND Analog Ground 18 DRVDD 3.3 V Digital Output Supply 41 AVDD 3.3 V Analog Supply 19 D0B Data Output Bit 0—Channel B (LSB) 42 S3 DCO Enable Select (Tie to AVDD for DCO 20 D1B Data Output Bit 1—Channel B Active) 21 D2B Data Output Bit 2—Channel B 43 DS− Data Sync Complement (If Unused, Tie to DRVDD) 22 D3B Data Output Bit 3—Channel B 44 DS+ Data Sync True (If Unused, Tie to DGND) 23 D4B Data Output Bit 4—Channel B 24 D5B Data Output Bit 5—Channel B Rev. 0 | Page 9 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS APPLICATIONS ANALOG INPUTS VOLTAGE REFERENCE Fixed Reference External Reference Programmable Reference CLOCKING THE AD9481 DS INPUTS DIGITAL OUTPUTS INTERLEAVING TWO AD9481s DATA CLOCK OUT POWER-DOWN INPUT AD9481 EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS GAIN OPTIONAL OPERATIONAL AMPLIFIER CLOCK OPTIONAL CLOCK BUFFER DS OPTIONAL XTAL VOLTAGE REFERENCE DATA OUTPUTS EVALUATION BOARD BILL OF MATERIALS (BOM) PCB SCHEMATICS PCB LAYERS OUTLINE DIMENSIONS ORDERING GUIDE