Datasheet AD9216 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| 页数 / 页 | 41 / 9 — Table 5. Parameter To. Rating. EXPLANATION OF TEST LEVELS. Table 6. Test … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.6 Mb |
| 文件语言 | 英语 |
Table 5. Parameter To. Rating. EXPLANATION OF TEST LEVELS. Table 6. Test Level. Description. ESD CAUTION
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文件文字版本
link to page 9 AD9216 ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter To Rating
may cause permanent damage to the device. This is a stress ELECTRICAL rating only and functional operation of the device at these or AVDD AGND −0.3 V to any other conditions above those indicated in the operational +3.9 V section of this specification is not implied. Exposure to absolute DRVDD DRGND −0.3 V to maximum rating conditions for extended periods may affect +3.9 V device reliability. AGND DRGND −0.3 V to +0.3 V
EXPLANATION OF TEST LEVELS
AVDD DRVDD −0.3 V to
Table 6.
+3.9 V
Test Level Description
Digital Outputs DRGND −0.3 V to DRVDD + I 100% production tested. 0.3 V II 100% production tested at 25°C and sample CLK_A, CLK_B, DCS, DFS, MUX_SELECT, AGND −0.3 V to tested at specified temperatures. OEB_A, OEB_B, SHARED_REF, AVDD + III Sample tested only. PDWN_A, PDWN_B 0.3 V IV Parameter is guaranteed by design and VIN−_A, VIN+_A, VIN−_B, VIN+_B AGND −0.3 V to characterization testing. AVDD + V Parameter is a typical value only. 0.3 V VI 100% production tested at 25°C; guaranteed by REFT_A, REFB_A,VREF, REFT_B, REFB_B, AGND −0.3 V to design and characterization testing for industrial SENSE AVDD + temperature range; 100% production tested at 0.3 V temperature extremes for military devices. ENVIRONMENTAL1 Operating Temperature −40°C to +85°C Junction Temperature 150°C Lead Temperature (10 sec) 300°C Storage Temperature −65°C to +150°C 1 Typical thermal impedances (64-lead LFCSP); θ JA = 26.4°C/W. These measurements were taken on a 4-layer board (with thermal via array) in still air, in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS LOGIC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS OUTPUT CODING TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Shared Reference Mode DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
Table 5.
Stresses above those listed under Absolute Maximum Ratings
Parameter To Rating
may cause permanent damage to the device. This is a stress ELECTRICAL rating only and functional operation of the device at these or AVDD AGND −0.3 V to any other conditions above those indicated in the operational +3.9 V section of this specification is not implied. Exposure to absolute DRVDD DRGND −0.3 V to maximum rating conditions for extended periods may affect +3.9 V device reliability. AGND DRGND −0.3 V to +0.3 V
EXPLANATION OF TEST LEVELS
AVDD DRVDD −0.3 V to
Table 6.
+3.9 V
Test Level Description
Digital Outputs DRGND −0.3 V to DRVDD + I 100% production tested. 0.3 V II 100% production tested at 25°C and sample CLK_A, CLK_B, DCS, DFS, MUX_SELECT, AGND −0.3 V to tested at specified temperatures. OEB_A, OEB_B, SHARED_REF, AVDD + III Sample tested only. PDWN_A, PDWN_B 0.3 V IV Parameter is guaranteed by design and VIN−_A, VIN+_A, VIN−_B, VIN+_B AGND −0.3 V to characterization testing. AVDD + V Parameter is a typical value only. 0.3 V VI 100% production tested at 25°C; guaranteed by REFT_A, REFB_A,VREF, REFT_B, REFB_B, AGND −0.3 V to design and characterization testing for industrial SENSE AVDD + temperature range; 100% production tested at 0.3 V temperature extremes for military devices. ENVIRONMENTAL1 Operating Temperature −40°C to +85°C Junction Temperature 150°C Lead Temperature (10 sec) 300°C Storage Temperature −65°C to +150°C 1 Typical thermal impedances (64-lead LFCSP); θ JA = 26.4°C/W. These measurements were taken on a 4-layer board (with thermal via array) in still air, in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS LOGIC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS OUTPUT CODING TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation Shared Reference Mode DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE