Datasheet AD7997, AD7998 (Analog Devices) - 7

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AD7997/AD7998 I2C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and tf measured between 0.3 VDD and 0.7 VDD. High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; TA =TMIN to TMAX.
Table 3. AD7997/AD7998 Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description
fSCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz High speed mode CB = 100 pF max 3.4 MHz CB = 400 pF max 1.7 MHz t1 Standard mode 4 µs tHIGH, SCL high time Fast mode 0.6 µs High speed mode CB = 100 pF max 60 ns CB = 400 pF max 120 ns t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs High speed mode CB = 100 pF max 160 ns CB = 400 pF max 320 ns t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns High speed mode 10 ns t 1 4 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs High speed mode CB = 100 pF max 0 702 ns CB = 400 pF max 0 150 ns t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs High speed mode 160 ns t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs High speed mode 160 ns t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for stop condition Fast mode 0.6 µs High speed mode 160 ns t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 80 ns CB = 400 pF max 20 160 ns Rev. 0 | Page 7 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS AD7997 SPECIFICATIONS AD7998 SPECIFICATIONS I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE ADDRESS POINTER REGISTER CONFIGURATION REGISTER CONVERSION RESULT REGISTER LIMIT REGISTERS DATAHIGH Register CH1/CH2/CH3/CH4 DATALOW Register CH1/CH2/CH3/CH4 Hysteresis Register (CH1/CH2/CH3/CH4) Using the Limit Registers to Store Min/Max Conversion Result ALERT STATUS REGISTER (CH1 TO CH4) CYCLE TIMER REGISTER SAMPLE DELAY AND BIT TRIAL DELAY SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7997/AD7998 WRITING TO THE ADDRESS POINTER REGISTER FOR A SUBSEQUENT REA WRITING A SINGLE BYTE OF DATA TO THE ALERT STATUS REGISTER O WRITING TWO BYTES OF DATA TO A LIMIT, HYSTERESIS, OR CONFIGU READING DATA FROM THE AD7997/AD7998 ALERT/BUSY PIN SMBus ALERT BUSY PLACING THE AD7997-1/AD7998-1 INTOHIGH SPEED MODE THE ADDRESS SELECT (AS) PIN MODES OF OPERATION MODE 1—USING THE PIN MODE 2 – COMMAND MODE MODE 3—AUTOMATIC CYCLE INTERVAL MODE OUTLINE DIMENSIONS ORDERING GUIDE RELATED PARTS IN I2C-COMPATIBLE ADC PRODUCT FAMILY