Datasheet AD7912, AD7922 (Analog Devices) - 7

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AD7912/AD7922 TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Limit at TMIN, Unit Description TMAX
f 1 SCLK 10 kHz min2 18 MHz max tCONVERT 16 × tSCLK AD7922 14 × tSCLK AD7912 tQUIET 30 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 15 ns min Minimum CS pulse width t2 10 ns min CS to SCLK setup time t 3 3 30 ns max Delay from CS until DOUT three-state is disabled t 3 4 45 ns max DOUT access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t 4 7 10 ns min SCLK to DOUT valid hold time t8 5 ns min DIN setup time prior to SCLK falling edge t9 6 ns min DIN hold time after SCLK falling edge t 5 10 30 ns max SCLK falling edge to DOUT three-state 10 ns min SCLK falling edge to DOUT three-state t 6 POWER-UP 1 µs max Power-up time from full power-down 1 Mark/space ratio for SCLK input is 40/60 to 60/40. 2 Minimum fSCLK at which specifications are guaranteed. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. 4 Measured with a 50 pF load capacitor. 5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See the Power-Up Time section.
TIMING DIAGRAMS t7 200
µ
A IOL SCLK TO OUTPUT 1.6V PIN CL V 50pF IH DOUT V 200
µ
A I IL OH
04351-0-004 04351-0-002 Figure 2. Load Circuit for Digital Output Timing Specifications Figure 4. Hold Time after SCLK Falling Edge
t4 t10 SCLK SCLK VIH 1.6V DOUT DOUT VIL
04351-0-003 04351-0-005 Figure 3. Access Time after SCLK Falling Edge Figure 5. SCLK Falling Edge to DOUT Three-State Rev. 0 | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7912 SPECIFICATIONS AD7922 SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS DIN INPUT DOUT OUTPUT MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME DAISY-CHAIN MODE DAISY-CHAIN EXAMPLE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7912/AD7922 to TMS320C541 Interface AD7912/AD7922 to ADSP-218x AD7912/AD7922 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING AD7912/AD7922 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE