Datasheet AD7457 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Pseudo Differential Input, 100 kSPS, 12-Bit ADC in 8-Lead SOT-23 |
| 页数 / 页 | 21 / 6 — AD7457. TIMING SPECIFICATIONS1. Table 2. Parameter. Limit at TMIN, TMAX. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 346 Kb |
| 文件语言 | 英语 |
AD7457. TIMING SPECIFICATIONS1. Table 2. Parameter. Limit at TMIN, TMAX. Unit. Description. POWER. CONVERT. START. TRACK. HOLD. TPOWERUP
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AD7457 TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 10 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 1.6 µs max t2 10 ns min CS rising edge to SCLK falling edge setup time t 3 3 20 ns max Delay from CS rising edge until SDATA three-state disabled t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK high pulse width t6 0.4 tSCLK ns min SCLK low pulse width t7 10 ns min SCLK edge to data valid hold time t 4 8 10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled t 5 POWER-UP 1 µs max Power-up time from full power-down tPOWER-DOWN 7.4 µs min Minimum time spent in power-down 1 The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figur an e 2 d the Serial Interface section. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for the output to cross 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5 See the Power Consumptio sect n ion.
POWER CONVERT UP START TRACK HOLD TRACK TPOWERUP TPOWERUP TACQUISITION TACQUISTION CS AUTOMATIC t POWER DOWN t 5 2 SCLK t t t 6 8 t3 4 t T 7 POWERDOWN SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE 03157-0-001 4 LEADING ZEROS
Figure 2. AD7457 Serial Interface Timing Diagram Rev. A | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SECTION SERIAL INTERFACE POWER CONSUMPTION MICROPROCESSOR INTERFACING AD7457 to ADSP-218x APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
AD7457 TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 10 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 1.6 µs max t2 10 ns min CS rising edge to SCLK falling edge setup time t 3 3 20 ns max Delay from CS rising edge until SDATA three-state disabled t 3 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK high pulse width t6 0.4 tSCLK ns min SCLK low pulse width t7 10 ns min SCLK edge to data valid hold time t 4 8 10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled t 5 POWER-UP 1 µs max Power-up time from full power-down tPOWER-DOWN 7.4 µs min Minimum time spent in power-down 1 The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figur an e 2 d the Serial Interface section. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for the output to cross 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 5 See the Power Consumptio sect n ion.
POWER CONVERT UP START TRACK HOLD TRACK TPOWERUP TPOWERUP TACQUISITION TACQUISTION CS AUTOMATIC t POWER DOWN t 5 2 SCLK t t t 6 8 t3 4 t T 7 POWERDOWN SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 THREE-STATE THREE-STATE 03157-0-001 4 LEADING ZEROS
Figure 2. AD7457 Serial Interface Timing Diagram Rev. A | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SECTION SERIAL INTERFACE POWER CONSUMPTION MICROPROCESSOR INTERFACING AD7457 to ADSP-218x APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE