Pseudo Differential Input, 100 kSPS, 12-Bit ADC in 8-Lead SOT-23
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21 /10 — AD7457. 4.0. VDD = 3V. 3.5. 3.0. SB). DD = 5V. 2.5. S T. (L 2.0. DNL N …
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AD7457. 4.0. VDD = 3V. 3.5. 3.0. SB). DD = 5V. 2.5. S T. (L 2.0. DNL N 1.5. E I 1.0. POSITIVE DNL. IVE NUMBER O. CHANG 0.5. CT E. F EF. –0.5. NEGATIVE DNL
AD74574.012VDD = 3V3.5113.0SB)V(LDD = 5V2.5S TSB)10BI(L 2.0FDNL N 1.59E I 1.0POSITIVE DNL8IVE NUMBER OCHANG 0.5CT E0F EF7–0.5NEGATIVE DNL–1.003157-0-020603157-0-02200.51.01.52.02.53.03.500.51.01.52.02.53.03.5VREF (V)VREF (V) Figure 11. Changes in DNL vs. VREF for VDD = 5 V Figure 13. ENOB vs. VREF for VDD = 3 V and 5 V 543SB)(L L2NI N E I1POSITIVE INLCHANG0NEGATIVE INL–1–203157-0-02100.51.01.52.02.53.03.5VREF (V) Figure 12. Change in INL vs. VREF for VDD = 5 V Rev. A | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SECTION SERIAL INTERFACE POWER CONSUMPTION MICROPROCESSOR INTERFACING AD7457 to ADSP-218x APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE