Datasheet AD7453 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Pseudo Differential, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23 |
| 页数 / 页 | 21 / 6 — AD7453. TIMING SPECIFICATIONS. Table 2. Parameter. Limit at TMIN, TMAX. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 429 Kb |
| 文件语言 | 英语 |
AD7453. TIMING SPECIFICATIONS. Table 2. Parameter. Limit at TMIN, TMAX. Unit. Description. tCONVERT. SCLK. tQUIET. SDATA. DB11. DB10. DB2. DB1. DB0
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AD7453 TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2 and the Serial Interface section. VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Description
f 1 SCLK 10 kHz min 10 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 1.6 µs max tQUIET 60 ns min Minimum quiet time between the end of a serial read and the next falling edge of CS t1 10 ns min Minimum CS pulse width t2 10 ns min CS falling edge to SCLK falling edge setup time t 2 3 20 ns max Delay from CS falling edge until SDATA three-state disabled t 2 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK high pulse width t6 0.4 tSCLK ns min SCLK low pulse width t7 10 ns min SCLK edge to data valid hold time t 3 8 10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled tPOWER-UP 4 1 µs max Power-up time from full power-down
t1 CS tCONVERT t2 t5 B SCLK 1 2 3 4 5 13 14 15 16 t6 t t 8 3 t t 7 4 tQUIET
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SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 4 LEADING ZEROS THREE-STATE
03155-A Figure 2. AD7453 Serial Interface Timing Diagram 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See Power-Up Time section. Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7453–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM THE ANALOG INPUT Analog Input Structure DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7453 to ADSP-21xx AD7453 to TMS320C5x/C54x AD7453 to DSP56xxx APPLICATION HINTS Grounding and Layout EVALUATING THE AD7453’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7453 TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2 and the Serial Interface section. VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Description
f 1 SCLK 10 kHz min 10 MHz max tCONVERT 16 × tSCLK tSCLK = 1/fSCLK 1.6 µs max tQUIET 60 ns min Minimum quiet time between the end of a serial read and the next falling edge of CS t1 10 ns min Minimum CS pulse width t2 10 ns min CS falling edge to SCLK falling edge setup time t 2 3 20 ns max Delay from CS falling edge until SDATA three-state disabled t 2 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK high pulse width t6 0.4 tSCLK ns min SCLK low pulse width t7 10 ns min SCLK edge to data valid hold time t 3 8 10 ns min SCLK falling edge to SDATA three-state enabled 35 ns max SCLK falling edge to SDATA three-state enabled tPOWER-UP 4 1 µs max Power-up time from full power-down
t1 CS tCONVERT t2 t5 B SCLK 1 2 3 4 5 13 14 15 16 t6 t t 8 3 t t 7 4 tQUIET
-002
SDATA 0 0 0 0 DB11 DB10 DB2 DB1 DB0 4 LEADING ZEROS THREE-STATE
03155-A Figure 2. AD7453 Serial Interface Timing Diagram 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See Power-Up Time section. Rev. B | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7453–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM THE ANALOG INPUT Analog Input Structure DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7453 to ADSP-21xx AD7453 to TMS320C5x/C54x AD7453 to DSP56xxx APPLICATION HINTS Grounding and Layout EVALUATING THE AD7453’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE