Datasheet AD7441, AD7451 (Analog Devices) - 9

AD7441/AD7451 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 8 V REF 1 DD V 8 V AD7441/ DD 1 REF AD7441/ V 7 SCLK IN+ 2 AD7451 SCLK 2 7 VIN+ AD7451 V 6 SDATA IN– 3 SDATA 3 6 V TOP VIEW
6
IN– TOP VIEW
5 -00 -00
GND 4 (Not to Scale) 5 CS
53
CS 4 (Not to Scale) 5 GND
53 31 31 0 0 Figure 5. 8-Lead MSOP Pin Configuration Figure 6. 8-Lead SOT-23 Pin Configuration
Table 5. Pin Function Descriptions Pin. No. MSOP SOT-23 Mnemonic Description
1 8 VREF Reference Input for the AD7441/AD7451. An external reference in the range of 100 mV to VDD must be applied to this input. The specified reference input is 2.5 V. This pin is decoupled to GND with a capacitor of at least 0.1 μF. 2 7 VIN+ Noninverting Analog Input. 3 6 VIN– Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc offset to provide a pseudo ground. 4 5 GND Analog Ground. Ground reference point for all circuitry on the AD7441/AD7451. All analog input signals and any external reference signal are referred to this GND voltage. 5 4 CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7441/AD7451 and framing the serial data transfer. 6 3 SDATA Serial Data, Logic Output. The conversion result from the AD7441/AD7451 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of con- version data, followed by two trailing zeros. In both cases, the output coding is straight (natural) binary. 7 2 SCLK Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. 8 1 VDD Power Supply Input. VDD is 2.7 V to 5.25 V. This supply is decoupled to GND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. Rev. D | Page 9 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE Power-Up Time POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7441/AD7451 to ADSP-21xx AD7441/AD7451 to TMS320C5x/C54x AD7441/AD7451 to DSP56xxx GROUNDING AND LAYOUT HINTS EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE