Datasheet AD7440, AD7450A (Analog Devices)

Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23 Data Sheet AD7440 /AD7450A FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 1 MSPS VDD Specified for VDD of 3 V and 5 V Low power at max throughput rate 4 mW max at 1 MSPS with 3 V supplies VIN+ 12-BIT 9.25 mW max at 1 MSPS with 5 V supplies T/H SUCCESSIVE APPROXIMATION VIN– Fully differential analog input ADC V Wide input bandwidth REF 70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays SCLK High speed serial interface SDATA AD7440/AD7450A CONTROL LOGIC SPI/QSPI™/MICROWIRE™/DSP compatible CS Power-down mode: 1 μA max
-001
8-lead SOT-23 and MSOP packages
03051-A
GND APPLICATIONS
Figure 1.
Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation Motor control
on the falling edge of CS; the conversion is also initiated at this
GENERAL DESCRIPTION
point. The SAR architecture of these parts ensures that there are The AD7440/AD7450A1 are 10-bit and 12-bit high speed, low no pipeline delays. The AD7440 and the AD7450A use advanced power, successive approximation (SAR) analog-to-digital design techniques to achieve very low power dissipation at high converters with a fully differential analog input. These parts throughput rates. operate from a single 3 V or 5 V power supply and use
PRODUCT HIGHLIGHTS
advanced design techniques to achieve very low power 1. Operation with either 3 V or 5 V power supplies. dissipation at throughput rates up to 1 MSPS. The SAR architecture of these parts ensures that there are no pipeline 2. High throughput with low power consumption. delays. With a 3 V supply, the AD7440/AD7450A offer 4 mW max power consumption for 1 MSPS throughput. The parts contain a low noise, wide bandwidth, differential 3. Fully differential analog input. track-and-hold amplifier (T/H) that can handle input frequencies up to 3.5 MHz. The reference voltage is applied 4. Flexible power/serial clock speed management. externally to the V The conversion rate is determined by the serial clock, REF pin and can be varied from 100 mV to 3.5 V depending on the power supply and what suits the allowing the power to be reduced as the conversion time application. The value of the reference voltage determines the is reduced through the serial clock speed increase. These common-mode voltage range of the part. With this truly parts also feature a shutdown mode to maximize power differential input structure and variable reference input, the efficiency at lower throughput rates. user can select a variety of input ranges and bias points. 5. Variable voltage reference input. The conversion process and data acquisition are controlled 6. No pipeline delay. using CS and the serial clock, allowing the device to interface 7. Accurate control of the sampling instant via a CS input and with microprocessors or DSPs. The input signals are sampled once-off conversion control. 1 Protected by U.S. Patent Number 6,681,332. 8. ENOB > eight bits typically with 100 mV reference.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY AD7440–SPECIFICATIONS AD7450A–SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE GROUNDING AND LAYOUT HINTS EVALUATING THE AD7440/AD7450A PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE