Datasheet AD7791 (Analog Devices) - 9

AD7791 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN Pin CS 2 AD7791 9 DOUT/RDY No. Mnemonic Function AIN(+) 3 TOP VIEW 8 VDD (Not to Scale) AIN(–) 4 7 GND
6 REFIN(–) Negative Reference Input. This reference
REF(+)
input can lie anywhere between GND and
5 6 REF(–)
VDD – 0.1 V. 04227-0-005 Figure 5. Pin Configuration 7 GND Ground Reference Point. 8 VDD Supply Voltage, 2.5 V to 5.25 V. 9 DOUT/RDY Serial Data Output/Data Ready Output.
Table 4. Pin Function Descriptions
DOUT/RDY serves a dual purpose . It functions
Pin
as a serial data output pin to access the output
No. Mnemonic Function
shift register of the ADC. The output shift reg- 1 SCLK Serial Clock Input for Data Transfers to and ister can contain data from any of the from the ADC. The SCLK has a Schmitt- on-chip data or control registers. In addition, triggered input, making the interface suita- DOUT/RDY operates as a data ready pin, ble for opto-isolated applications. The serial going low to indicate the completion of a clock can be continuous with all data conversion. If the data is not read after the transmitted in a continuous train of pulses. conversion, the pin will go high before the Alternatively, it can be a noncontinuous next update occurs. clock with the information being trans- The DOUT/RDY falling edge can be used as an mitted to or from the ADC in smaller interrupt to a processor, indicating that valid batches of data. data is available. With an external serial clock, 2 CS Chip Select Input. This is an active low logic the data can be read using the DOUT/RDY pin. input used to select the ADC. CS can be With CS low, the data/control word informa- used to select the ADC in systems with tion is placed on the DOUT/RDY pin on the more than one device on the serial bus or as SCLK falling edge and is valid on the SCLK a frame synchronization signal in communi- rising edge. cating with the device. CS can be hardwired The end of a conversion is also indicated by low, allowing the ADC to operate in 3-wire the RDY bit in the status register. When CS is mode with SCLK, DIN, and DOUT used to high, the DOUT/RDY pin is three-stated but interface with the device. the RDY bit remains active. 3 AIN(+) Analog Input. AIN(+) is the positive terminal 10 DIN Serial Data Input to the Input Shift Register of the fully differential analog input. on the ADC. Data in this shift register is trans- 4 AIN(–) Analog Input. AIN(–) is the negative termi- ferred to the control registers within nal of the fully differential analog input. the ADC, the register selection bits of the 5 REFIN(+) Positive Reference Input. REFIN(+) can lie communications register identifying the anywhere between VDD and GND + 0.1 V. appropriate register. The nominal reference voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a reference from 0.1 V to VDD. Rev. A | Page 8 of 20 Document Outline AD7791—Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x8C) Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02) Filter Register (RS1, RS0 = 1, 0; Power-on/Reset = 0x04) Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Outline Dimensions Ordering Guide