Datasheet AD7679 (Analog Devices) - 5

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AD7679 Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS Logic Levels VIL –0.3 +0.8 V VIH 2.0 DVDD + 0.3 V IIL –1 +1 μA IIH –1 +1 μA DIGITAL OUTPUTS Data Format5 Pipeline Delay6 VOL ISINK = 1.6 mA 0.4 V VOH ISOURCE = –500 μA OVDD – 0.6 V POWER SUPPLIES Specified Performance AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 DVDD + 0.37 V Operating Current 500 kSPS Throughput AVDD PDBUF High 10.8 mA DVDD8 4.5 mA OVDD8 50 μA POWER DISSIPATION8 PDBUF High @ 500 kSPS 76 90 mW PDBUF High @ 1 kSPS 150 μW PDBUF Low @ 500 kSPS 89 103 mW TEMPERATURE RANGE9 Specified Performance TMIN to TMAX –40 +85 °C 1 See Analog Inputs section. 2 LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV. 3 See Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used. 4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 5 Parallel or Serial 18-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 Tested in Parallel Reading mode. 9 Contact factory for extended temperature range. Rev. A | Page 4 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7679’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE