Datasheet AD7679 (Analog Devices) - 9

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AD7679 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN F ND D BUF G D F ND F F DBU + – P AV RE NC AG IN NC NC NC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND PIN 1 AVDD 2 IDENTIFIER 35 CNVST MODE0 3 34 PD MODE1 4 33 RESET 5 D0/OB/2C 32 CS NC 6 AD7679 31 RD TOP VIEW NC 7 30 (Not to Scale) DGND D1/A0 8 29 BUSY D2/A1 9 28 D17 D3 10 27 D16 11 D4/DIVSCLK[0] 26 D15 D5/DIVSCLK[1] 12 25 D14 13 14 15 16 17 18 19 20 21 22 23 24 C K D D D T K R N L IN D D ND U L NC /INT O Y D T O Y S S X OV DV DG D S RR V VSC OGN /SC E S 1 /IN /IN RDC/ D1 D12/ D6/ 7 8 RDE D D D10/ D9/ NOTES D13/ 1. NC = NO CONNECT. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES HOWEVER,
04 0
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED
5- 08
THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF THE SYSTEM.
03 Figure 4.
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 44 AGND P Analog Power Ground Pin. 2, 47 AVDD P Input Analog Power Pins. Nominally 5 V. 3 MODE0 DI Data Output Interface Mode Selection. 4 MODE1 DI Data Output Interface Mode Selection:
Interface MODE MODE1 MODE0 Description
0 0 0 18-Bit Interface 1 0 1 16-Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface 5 D0/OB/2C DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6, 7, 40– NC No Connect. 42, 45 8 D1/A0 DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 9 D2/A1 DI/O When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. 10 D3 DO In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. 11, 12 D[4:5]or DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. DIVSCLK[0:1] When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. Rev. A | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS LAYOUT EVALUATING THE AD7679’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE