Datasheet AD7653 (Analog Devices) - 9

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AD7653 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN F ND FBUF ND ND ND FG F PIN 1 IDENTIFIER PDBUF PDRE RE TEMP AVDD IN AG AG NC ING RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND AVDD 2 35 CNVST NC 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS WARP 6 AD7653 31 RD IMPULSE 7 TOP VIEW 30 DGND SER/PAR (Not to Scale) 8 29 BUSY D0 9 28 D15 D1 10 27 D14 D2/DIVSCLK0 11 26 D13 D3/DIVSCLK1 12 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 T K N D K DD ND UT R SYNC SCL SDI VDD OGN O DV DG SCL SYNC RRO EXT/IN SDO INV INV RDC/ D9/ D10/ D4/ D8/ RDE D5/ D6/ D7/ 11/ D NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE LFCSP PACKAGE HAS AN EXPOSED PAD. THIS EPAD CAN BE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET ELECTRICAL PERFORMANCE SPECIFICATIONS.
02966-0-002 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
0 EPAD Exposed Pad. The LFCSP package has an exposed pad. This EPAD can be connected to AGND. This connection is not required to meet electrical performance specifications. 1, 36, AGND P Analog Power Ground Pin. 41, 42 2, 44 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 40 NC No Connect. 4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6 WARP DI Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. Rev. B | Page 8 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Hightlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Definitions of Specifications Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Reference Voltage Temperature Coefficient Typical Performance Characteristics Circuit Information Converter Operation Modes of Operation Transfer Functions Typical Connection Diagram Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply Power Dissipation vs. Throughput Conversion Control Digital Interface Parallel Interface Serial Interface Master Serial Interface Internal Clock Slave Serial Interface External Clock External Discontinuous Clock Data Read After Conversion External Clock Data Read During Conversion Microprocessor Interfacing SPI Interface (ADSP-2191M) Application Hints Bipolar and Wider Input Ranges Layout Outline Dimensions Ordering Guide