Datasheet AD7910, AD7920 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 250 kSPS, 12- Bit ADC in 6 Lead SC70 |
| 页数 / 页 | 24 / 6 — AD7910/AD7920. TIMING SPECIFICATIONS. Table 3. Parameter1. Limit at TMIN, … |
| 修订版 | C |
| 文件格式/大小 | PDF / 498 Kb |
| 文件语言 | 英语 |
AD7910/AD7920. TIMING SPECIFICATIONS. Table 3. Parameter1. Limit at TMIN, TMAX. Unit. Description. 200. IOL. TO OUTPUT. 1.6V. PIN. 50pF. IOH
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AD7910/AD7920 TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 3. AD7910/AD7920 Parameter1 Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min3 5 MHz max tCONVERT 14 × tSCLK AD7910 16 × tSCLK AD7920 tQUIET 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 ns min Minimum CS pulse width t2 10 ns min CS to SCLK setup time t 4 3 22 ns max Delay from CS until SDATA three-state disabled t4 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t 5, 6 7 SCLK to data valid hold time 10 ns min VDD ≤ 3.3 V 9.5 ns min 3.3 V < VDD ≤ 3.6 V 7 ns min VDD > 3.6 V t 6, 7 8 36 ns max SCLK falling edge to SDATA three-state See Note 7 ns min SCLK falling edge to SDATA three-state t 8 POWER-UP 1 μs max Power-up time from full power-down 1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V. 5 Measured with a 50 pF load capacitor. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, shown in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading. 7 T7 values apply to t8 minimum values also. 8 See Power-Up Time section.
200
μ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
μ
A IOH
02976-002 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. C | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7910 AD7920 TIMING SPECIFICATIONS TIMING EXAMPLES TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7910/AD7920 TO TMS320C541 INTERFACE AD7910/AD7920 TO ADSP-218x AD7910/AD7920 TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7910/AD7920 TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 3. AD7910/AD7920 Parameter1 Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min3 5 MHz max tCONVERT 14 × tSCLK AD7910 16 × tSCLK AD7920 tQUIET 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 ns min Minimum CS pulse width t2 10 ns min CS to SCLK setup time t 4 3 22 ns max Delay from CS until SDATA three-state disabled t4 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK ns min SCLK high pulse width t 5, 6 7 SCLK to data valid hold time 10 ns min VDD ≤ 3.3 V 9.5 ns min 3.3 V < VDD ≤ 3.6 V 7 ns min VDD > 3.6 V t 6, 7 8 36 ns max SCLK falling edge to SDATA three-state See Note 7 ns min SCLK falling edge to SDATA three-state t 8 POWER-UP 1 μs max Power-up time from full power-down 1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V. 5 Measured with a 50 pF load capacitor. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, shown in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading. 7 T7 values apply to t8 minimum values also. 8 See Power-Up Time section.
200
μ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
μ
A IOH
02976-002 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. C | Page 6 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7910 AD7920 TIMING SPECIFICATIONS TIMING EXAMPLES TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7910/AD7920 TO TMS320C541 INTERFACE AD7910/AD7920 TO ADSP-218x AD7910/AD7920 TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE