Datasheet AD7734 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 4-Channel, ±10 V Input Range, High Throughput, 24-Bit Sigma-Delta A/D Converter |
| 页数 / 页 | 33 / 10 — Data Sheet. AD7734. TYPICAL PERFORMANCE CHARACTERISTICS. 300. CHOP = 1. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 711 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7734. TYPICAL PERFORMANCE CHARACTERISTICS. 300. CHOP = 1. MCLK = 6.144MHz. 250. ES 22. 200. OD 21. G C. – ppm 150. SIN 20. O M. 100
该数据表的模型线
文件文字版本
Data Sheet AD7734 TYPICAL PERFORMANCE CHARACTERISTICS 25 300 24 CHOP = 1 MCLK = 6.144MHz 250 23 ES 22 200 OD 21 G C – ppm 150 SIN 20 L IS IN O M 100 N 19 18 50 17 16 0
005
1 2 3 4 5 6 7 8 9 10 –20 –15 –10 –5 0 5 10 15 20
008
FILTER WORD
03071-
AIN DIFFERENTIAL VOLTAGE – V
03071- Figure 5. No Missing Codes Performance, Chopping Enabled Figure 8. Typical INL vs. AIN Voltage, AIN Range =±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = O V
25 300 24 CHOP = 0 MCLK = 6.144MHz 250 23 ES 22 200 OD 21 G C ppm SIN 150 20 – IS L IN O M N 19 100 18 50 17 16
006
1 2 3 4 5 6 7 8 9 10 0
009
–20 –15 –10 –5 0 5 10 15 20
03071-
FILTER WORD
03071-
AIN DIFFERENTIAL VOLTAGE – V
Figure 6. No Missing Codes Performance, Chopping Disabled Figure 9. Typical INL vs. AIN Voltage, AIN Range = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V
30 20 25 A 15 20 – m NT – ppm 15 L CURRE 10 IN DD 10 DV + 5 5 AV DD 0 0 1 2 3 4 5 6 7 0
007 010
0 1 2 3 4 5 6 7 MCLK FREQUENCY – MHz
03071- 03071-
MCLK FREQUENCY – MHz
Figure 7. Typical INL vs. MCLK Frequency, Figure 10. Typical Supply Current vs. MCLK Frequency, AIN = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V Normal Operation, Converting Rev. B | Page 9 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REGISTER DESCRIPTION REGISTER ACCESS COMMUNICATIONS REGISTER I/O PORT REGISTER REVISION REGISTER TEST REGISTER ADC STATUS REGISTER CHECKSUM REGISTER ADC ZERO-SCALE CALIBRATION REGISTER ADC FULL-SCALE REGISTER CHANNEL DATA REGISTERS CHANNEL ZERO-SCALE CALIBRATION REGISTERS CHANNEL FULL-SCALE CALIBRATION REGISTERS CHANNEL STATUS REGISTERS CHANNEL SETUP REGISTERS CHANNEL CONVERSION TIME REGISTERS MODE REGISTER DIGITAL INTERFACE DESCRIPTION HARDWARE RESET ACCESS THE AD7734 REGISTERS SINGLE CONVERSION AND READING DATA DUMP MODE CONTINUOUS CONVERSION MODE CONTINUOUS READ (CONTINUOUS CONVERSION) MODE CIRCUIT DESCRIPTION ANALOG FRONT END ANALOG INPUT’S EXTENDED VOLTAGE RANGE CHOPPING MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING Σ-Δ ADC FREQUENCY RESPONSE VOLTAGE REFERENCE INPUTS REFERENCE DETECT I/O PORT CALIBRATION ADC ZERO-SCALE SELF-CALIBRATION PER CHANNEL SYSTEM CALIBRATION OUTLINE DIMENSIONS ORDERING GUIDE
005
1 2 3 4 5 6 7 8 9 10 –20 –15 –10 –5 0 5 10 15 20
008
FILTER WORD
03071-
AIN DIFFERENTIAL VOLTAGE – V
03071- Figure 5. No Missing Codes Performance, Chopping Enabled Figure 8. Typical INL vs. AIN Voltage, AIN Range =±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = O V
25 300 24 CHOP = 0 MCLK = 6.144MHz 250 23 ES 22 200 OD 21 G C ppm SIN 150 20 – IS L IN O M N 19 100 18 50 17 16
006
1 2 3 4 5 6 7 8 9 10 0
009
–20 –15 –10 –5 0 5 10 15 20
03071-
FILTER WORD
03071-
AIN DIFFERENTIAL VOLTAGE – V
Figure 6. No Missing Codes Performance, Chopping Disabled Figure 9. Typical INL vs. AIN Voltage, AIN Range = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V
30 20 25 A 15 20 – m NT – ppm 15 L CURRE 10 IN DD 10 DV + 5 5 AV DD 0 0 1 2 3 4 5 6 7 0
007 010
0 1 2 3 4 5 6 7 MCLK FREQUENCY – MHz
03071- 03071-
MCLK FREQUENCY – MHz
Figure 7. Typical INL vs. MCLK Frequency, Figure 10. Typical Supply Current vs. MCLK Frequency, AIN = ±10 V, BIAS0 to BIAS3, BIASHI = 2.5 V, BIASLO = 0 V Normal Operation, Converting Rev. B | Page 9 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REGISTER DESCRIPTION REGISTER ACCESS COMMUNICATIONS REGISTER I/O PORT REGISTER REVISION REGISTER TEST REGISTER ADC STATUS REGISTER CHECKSUM REGISTER ADC ZERO-SCALE CALIBRATION REGISTER ADC FULL-SCALE REGISTER CHANNEL DATA REGISTERS CHANNEL ZERO-SCALE CALIBRATION REGISTERS CHANNEL FULL-SCALE CALIBRATION REGISTERS CHANNEL STATUS REGISTERS CHANNEL SETUP REGISTERS CHANNEL CONVERSION TIME REGISTERS MODE REGISTER DIGITAL INTERFACE DESCRIPTION HARDWARE RESET ACCESS THE AD7734 REGISTERS SINGLE CONVERSION AND READING DATA DUMP MODE CONTINUOUS CONVERSION MODE CONTINUOUS READ (CONTINUOUS CONVERSION) MODE CIRCUIT DESCRIPTION ANALOG FRONT END ANALOG INPUT’S EXTENDED VOLTAGE RANGE CHOPPING MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING Σ-Δ ADC FREQUENCY RESPONSE VOLTAGE REFERENCE INPUTS REFERENCE DETECT I/O PORT CALIBRATION ADC ZERO-SCALE SELF-CALIBRATION PER CHANNEL SYSTEM CALIBRATION OUTLINE DIMENSIONS ORDERING GUIDE