Datasheet AD7738 (Analog Devices) - 5

AD7738 TIMING SPECIFICATIONS1, 2, 3 (AVDD = 5 V 5%; DVDD = 2.7 V to 3.6 V or 5 V 5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comment
MASTER CLOCK RANGE 1 6.144 MHz t1 50 ns SYNC Pulsewidth t2 500 ns RESET Pulsewidth READ OPERATION t4 0 ns CS Falling Edge to SCLK Falling Edge Setup Time t 4 5 SCLK Falling Edge to Data Valid Delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t 4, 5 CS 5A Falling Edge to Data Valid Delay 0 60 ns DVDD of 4.75 V to 5.25 V 0 80 ns DVDD of 2.7 V to 3.3 V t6 50 ns SCLK High Pulsewidth t7 50 ns SCLK Low Pulsewidth t8 0 ns CS Rising Edge after SCLK Rising Edge Hold Time t 6 9 10 80 ns Bus Relinquish Time after SCLK Rising Edge WRITE OPERATION t11 0 ns CS Falling Edge to SCLK Falling Edge Setup t12 30 ns Data Valid to SCLK Rising Edge Setup Time t13 25 ns Data Valid after SCLK Rising Edge Hold Time t14 50 ns SCLK High Pulsewidth t15 50 ns SCLK Low Pulsewidth t16 0 ns CS Rising Edge after SCLK Rising Edge Hold Time NOTES 1Sample tested during initial release to ensure compliance. 2All input signals are specified with tr = tf = 5 ns (10% to 90% of DV ) and timed from a voltage level of 1.6 V. DD 3See Figures 1 and 2. 4These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V or V limits. OL OH 5This specification is relevant only if CS goes low while SCLK is low. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications are subject to change without notice. –4– REV. 0 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS