Datasheet AD7738 (Analog Devices) - 7

AD7738 ABSOLUTE MAXIMUM RATINGS*
Operating Temperature Range . –40C to +105C (T Storage Temperature Range . –65C to +150C A = 25C unless otherwise noted.) AVDD to AGND, DVDD to DGND . –0.3 V to +7 V Junction Temperature . 150C AGND to DGND . –0.3 V to +0.3 V TSSOP Package, Power Dissipation . 660 mW AVDD to DVDD . –5 V to +5 V ␪JA Thermal Impedance . 97.9C/W AIN, AINCOM to AGND . –0.3 V to AVDD + 0.3 V Lead Temperature, Soldering REFIN(+), REFIN(–) to AGND . –0.3 V to AVDD + 0.3 V Vapor Phase (60 sec) . 215C MUXOUT(+) to AGND . –0.3 V to AVDD + 0.3 V Infrared (15 sec) . 220C MUXOUT(–) to AGND . –0.3 V to AVDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause perma- ADCIN(+), ADCIN(–) to AGND . –0.3 V to AVDD + 0.3 V nent damage to the device. This is a stress rating only; functional operation of the P1 Voltage to AGND . –0.3 V to AV device at these or any other conditions above those indicated in the operational DD + 0.3 V Digital Input Voltage to DGND . –0.3 V to AV section of this specification is not implied. Exposure to absolute maximum rating DD + 0.3 V conditions for extended periods may affect device reliability. Digital Output Voltage to DGND . –0.3 V to AVDD + 0.3 V
ORDERING GUIDE Temperature Package Package Model Range Description Options
AD7738BRU –40C to +105C TSSOP 28 RU-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7738 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
MUXOUT ADCIN REFIN– REFIN+ REFERENCE AIN0 DETECT AIN1 BUFFER AIN2 AIN3 24-BIT MUX - ADC AIN4 AIN5 DVDD AIN6 AD7738 AIN7 CS CALIBRATION SERIAL SCLK AINCOM/P0 CIRCUITRY INTERFACE DOUT DIN AVDD RDY CLOCK CONTROL I/O PORT GENERATOR LOGIC SYNC/P1 RESET AGND AV MCLKOUT MCLKIN DGND DV DD DD
Figure 4. Block Diagram –6– REV. 0 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS