Datasheet AD7485 (Analog Devices) - 4

AD7485 Parameter Specification Unit Test Conditions/Comments
POWER REQUIREMENTS VDD 5 V ±5% VDRIVE 2.7 V min 5.25 V max IDD Normal Mode (Static) 13 mA max Normal Mode (Operational) 17 mA max NAP Mode 0.6 mA max STANDBY Mode8 2 µA max 0.5 µA typ Power Dissipation Normal Mode (Operational) 85 mW max NAP Mode 3 mW max STANDBY Mode8 10 µW max NOTES 1Temperature ranges as follows: –40°C to +85°C. 2SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB. 3See Typical Performance Characteristics section for analog input circuits used. 4See Terminology. 5Sample tested @ 25°C to ensure compliance. 6Current drawn from external reference during conversion. 7ILOAD = 200 µA. 8Digital input levels at GND or VDRIVE. Specifications subject to change without notice.
TIMING CHARACTERISTICS1 (VDD = 5 V 5%, AGND = DGND = 0 V, VREF = External; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit
Master Clock Frequency fMCLK 0.01 25 MHz MCLK Period t1 40 100000 ns Conversion Time t2 t1 24 ns CONVST Low Period (Mode 1)2 t3 t1 22 ns CONVST High Period (Mode 1)2 t4 10 ns MCLK High Period t5 0.4 t1 0.6 t1 ns MCLK Low Period t6 0.4 t1 0.6 t1 ns CONVST Falling Edge to MCLK Rising Edge t7 7 ns MCLK Rising Edge to MSB Valid t8 15 ns Data Valid before SCO Falling Edge t9 10 ns Data Valid after SCO Falling Edge t10 20 ns CONVST Rising Edge to SDO Three-State t11 6 ns CONVST Low Period (Mode 2)2 t12 10 t1 2 ns CONVST High Period (Mode 2)3 t13 10 ns CONVST Falling Edge to TFS Falling Edge t14 10 ns TFS Falling Edge to MSB Valid t15 30 ns TFS Rising Edge to SDO Three-State t16 8 ns TFS Low Period4 t17 t1 22 ns TFS High Period4 t18 10 ns MCLK Fall Time t19 5 25 ns MCLK Rise Time t20 5 25 ns MCLK – SCO Delay t21 6 25 ns NOTES 1All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2CONVST idling high. See Serial Interface section for further details. 3CONVST idling low. See Serial Interface section for further details. 4TFS can also be tied low in this mode. Specifications subject to change without notice. REV. A –3– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track/Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Typical Performance Characteristics CIRCUIT DESCRIPTION CONVERTER OPERATION ADC TRANSFER FUNCTION POWER SAVING SERIAL INTERFACE Driving the CONVST Pin Board Layout and Grounding OUTLINE DIMENSIONS