Datasheet AD7476A, AD7477A, AD7478A (Analog Devices) - 8

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AD7476A/AD7477A/AD7478A Data Sheet TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4. Parameter Limit at TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min3 A, B grades 20 kHz min3 Y grade 20 MHz max tCONVERT 16 × tSCLK AD7476A 14 × tSCLK AD7477A 12 × tSCLK AD7478A tQUIET 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 ns min Minimum CS pulse width t2 10 ns min CS to SCLK setup time t 4 3 22 ns max Delay from CS until SDATA three-state disabled t 4 4 40 ns max Data access time after SCLK falling edge t5 0.4 tSCLK ns min SCLK low pulse width t6 0.4 tSCLK ns min SCLK high pulse width t 5 7 SCLK to data valid hold time 10 ns min VDD ≤ 3.3 V 9.5 ns min 3.3 V < VDD ≤ 3.6 V 7 ns min VDD > 3.6 V t 6 8 36 ns max SCLK falling edge to SDATA high impedance t7 values also apply to t8 minimum values ns min SCLK falling edge to SDATA high impedance t 7 POWER-UP 1 μs max Power-up time from full power-down 1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 Measured with the load circuit shown in Figure 2, and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V, and 0.8 V or 2.0 V for VDD > 2.35 V. 5 Measured with a 50 pF load capacitor. 6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. Therefore, the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See the Power-Up Time section. Rev. G | Page 8 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7476A SPECIFICATIONS AD7477A SPECIFICATIONS AD7478A SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION THE CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7476A/AD7477A/AD7478A TO ADSP-2181 INTERFACE AD7476A/AD7477A/AD7478A TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS