Datasheet AD7650 (Analog Devices) - 5

AD7650 TIMING SPECIFICATIONS (continued) Parameter Symbol Min Typ Max Unit
REFER TO FIGURES 13 AND 14 (continued) SCLK Last Edge to SYNC Delay t24 3 CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read After Convert t28 2.75/3/3.25 µs (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to SYNC Asserted Delay t29 1/1.25/1.5 µs (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay t30 50 ns REFER TO FIGURES 15 AND 16 (Slave Serial Interface Modes)2 External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 16 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice.
1.6mA IOL TO OUTPUT 1.4V PIN CL 60pF* 2V 500 I
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A OH 0.8V t t DELAY DELAY *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD 2V 2V CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. 0.8V 0.8V
Figure 1. Load Circuit for Digital Interface Timing, Figure 2. Voltage Reference Levels for Timing SDOUT, SYNC, SCLK Outputs, CL = 10 pF REV. 0 –4–