Datasheet AD9433 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 12-Bit 105/125 MSPS Analog-To-Digital IF Sampling Converter |
| 页数 / 页 | 21 / 10 — AD9433. 11.3. IMD3 = 92dBFS. –10. –20. 10.9. –30. 10.6. –40. SNR. SINAD. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 438 Kb |
| 文件语言 | 英语 |
AD9433. 11.3. IMD3 = 92dBFS. –10. –20. 10.9. –30. 10.6. –40. SNR. SINAD. –50. 10.3. –60. INAD (. 9.9. –70. NR/. –80. 9.6. –90. –100. 9.3. –110. –120. 8.9. 7.5. 15.0. 22.5. 30.0
该数据表的模型线
文件文字版本
AD9433 0 69 11.3 IMD3 = 92dBFS –10 –20 67 10.9 –30 ) 65 10.6 S –40 SNR BF B) SINAD d –50 d s) ( 63 10.3 it E B –60 ( UD INAD ( IT S OB 9.9 L –70 61 N P NR/ E –80 S AM 59 9.6 –90 –100 57 9.3 –110 –120
5
55 8.9
18
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
01
10.3 49.3 80.3 170.3 250.3
0 7- 7-
FREQUENCY (MHz)
97
AIN (MHz)
97 01 01 Figure 10. FFT: fS = 105 MSPS, fIN = 49.3 MHz and 50.3 MHz, Figure 13. SNR/SINAD and ENOB vs. AIN Frequency, Differential AIN @ −0.5 dBFS, Differential AIN @ −7 dBFS for Each Tone, SFDR Mode Enabled fS = 125 MSPS, SFDR Mode Enabled
110 100 100 SFDR (dBc) 90 THIRD HARMONIC 90 80 B) d SECOND HARMONIC 80 SNR (dBFS) ( E 70 70 B) SNR d ANC 60 60 RM DR ( O F 50 S 50 SFDR (dBFS) RF R/ E N 40 40 S IC P 30 30 NAM Y 20 D 20 90dBFS 10 REFERENCE 10 0
6
0
9
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
01
3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5
01 7- 7-
AIN LEVEL (dBFS)
97
AIN COMMON-MODE VOLTAGE (V)
97 01 01 Figure 11. SNR and SFDR vs. AIN Level, fS = 105 MSPS, fIN = 49.3 MHz, Figure 14. Dynamic Performance vs. AIN Common-Mode Voltage, Differential AIN, SFDR Mode Enabled Differential AIN @ −0.5 dBFS, fIN = 49.3 MHz, fS = 105 MSPS
110 69 68 100 67 ) B 90 (d 66 ) –40°C IMD B R 65 d E 80 ( D R 64 -OR SN +25°C D IR 70 63 H T 62 60 +85°C 61 50 60
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
17 2 0
10.3 49.3 80.3 170.3 250.3
0 7- 7-
AIN LEVEL (dBFS)
97
AIN (MHz)
97 01 01 Figure 12. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 49.3 MHz Figure 15. SNR vs. AIN Frequency over Temperature, fS = 105 MSPS, and 50.3 MHz, Differential AIN, SFDR Mode Enabled Differential AIN, SFDR Mode Disabled Rev. A | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL INTRODUCTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY EQUIVALENT CIRCUITS THEORY OF OPERATION ENCODE INPUT ENCODE VOLTAGE LEVEL DEFINITION ANALOG INPUT SFDR OPTIMIZATION DIGITAL OUTPUTS VOLTAGE REFERENCE TIMING APPLICATIONS INFORMATION LAYOUT INFORMATION REPLACING THE AD9432 WITH THE AD9433 OUTLINE DIMENSIONS ORDERING GUIDE
5
55 8.9
18
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
01
10.3 49.3 80.3 170.3 250.3
0 7- 7-
FREQUENCY (MHz)
97
AIN (MHz)
97 01 01 Figure 10. FFT: fS = 105 MSPS, fIN = 49.3 MHz and 50.3 MHz, Figure 13. SNR/SINAD and ENOB vs. AIN Frequency, Differential AIN @ −0.5 dBFS, Differential AIN @ −7 dBFS for Each Tone, SFDR Mode Enabled fS = 125 MSPS, SFDR Mode Enabled
110 100 100 SFDR (dBc) 90 THIRD HARMONIC 90 80 B) d SECOND HARMONIC 80 SNR (dBFS) ( E 70 70 B) SNR d ANC 60 60 RM DR ( O F 50 S 50 SFDR (dBFS) RF R/ E N 40 40 S IC P 30 30 NAM Y 20 D 20 90dBFS 10 REFERENCE 10 0
6
0
9
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
01
3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5
01 7- 7-
AIN LEVEL (dBFS)
97
AIN COMMON-MODE VOLTAGE (V)
97 01 01 Figure 11. SNR and SFDR vs. AIN Level, fS = 105 MSPS, fIN = 49.3 MHz, Figure 14. Dynamic Performance vs. AIN Common-Mode Voltage, Differential AIN, SFDR Mode Enabled Differential AIN @ −0.5 dBFS, fIN = 49.3 MHz, fS = 105 MSPS
110 69 68 100 67 ) B 90 (d 66 ) –40°C IMD B R 65 d E 80 ( D R 64 -OR SN +25°C D IR 70 63 H T 62 60 +85°C 61 50 60
0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
17 2 0
10.3 49.3 80.3 170.3 250.3
0 7- 7-
AIN LEVEL (dBFS)
97
AIN (MHz)
97 01 01 Figure 12. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 49.3 MHz Figure 15. SNR vs. AIN Frequency over Temperature, fS = 105 MSPS, and 50.3 MHz, Differential AIN, SFDR Mode Enabled Differential AIN, SFDR Mode Disabled Rev. A | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL INTRODUCTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY EQUIVALENT CIRCUITS THEORY OF OPERATION ENCODE INPUT ENCODE VOLTAGE LEVEL DEFINITION ANALOG INPUT SFDR OPTIMIZATION DIGITAL OUTPUTS VOLTAGE REFERENCE TIMING APPLICATIONS INFORMATION LAYOUT INFORMATION REPLACING THE AD9432 WITH THE AD9433 OUTLINE DIMENSIONS ORDERING GUIDE