Datasheet AD7783 (Analog Devices) - 9

AD7783 NOISE PERFORMANCE MASTER MODE (MODE = 0)
Table I shows the output rms noise and output peak-to-peak In this mode, SCLK is provided by the AD7783. With CS low, resolution in bits (rounded to the nearest 0.5 LSB) for the two SCLK becomes active when a conversion is complete and gener- input voltage ranges. The numbers are typical and are generated ates 24 falling and rising edges. The DOUT/RDY pin, which is at a differential input voltage of 0 V. The peak-to-peak reso- normally high, goes low to indicate that a conversion is complete. lution figures represent the resolution for which there will be Data is output on the DOUT/RDY pin following the SCLK no code flicker within a six-sigma limit. The output noise comes falling edge and is valid on the SCLK rising edge. When the from two sources. The first is the electrical noise in the semi- 24-bit word has been output, SCLK idles high until the next conductor devices (device noise) used in the implementation of conversion is complete. DOUT/RDY returns high and will remain the modulator. Secondly, when the analog input is converted high until another conversion is available. It then operates as a into the digital domain, quantization noise is added. The device RDY signal again. The part will continue to convert until CS is noise is at a low level and is independent of frequency. The taken high. SCLK and DOUT/RDY are three-stated when CS is quantization noise starts at an even lower level but rises rapidly taken high. with increasing frequency to become the dominant noise source.
SLAVE MODE (MODE = 1) Table I. Typical Output RMS Noise and
In slave mode, the SCLK is generated externally. SCLK must
Peak-to-Peak Resolution vs. Input Range
idle high between data transfers. With CS low, DOUT/RDY goes low when a conversion is complete. Twenty-four SCLK
Input Range
pulses are needed to transfer the digital word from the AD7783. ±
160 mV
±
2.56 V
Twenty-four consecutive pulses can be generated or, alterna- tively, the data transfer can be split into batches. This is useful Noise (mV) 0.65 2.30 when interfacing to a microcontroller that uses 8-bit transfers. Peak-to-Peak Resolution (Bits) 16.5 18.5 Data is output following the SCLK falling edge and is valid on the SCLK rising edge.
DIGITAL INTERFACE
The AD7783’s serial interface consists of four signals: CS,
CIRCUIT DESCRIPTION
SCLK, DOUT/RDY, and MODE. The MODE pin is used to
Analog Input Channel
select the master/slave mode of operation. When the part is The ADC has one fully differential input channel. It feeds into a configured as a master, SCLK is an output; SCLK is an input high impedance input stage of the buffer amplifier. As a result, when slave mode is selected. Data transfers take place with the ADC input can handle significant source impedances and is respect to this SCLK signal. The DOUT/RDY line is used tailored for direct connection to external resistive-type sensors, for accessing data from the data register. This pin also functions such as strain gages or resistance temperature detectors (RTDs). as a RDY line. When a conversion is complete, DOUT/RDY The absolute input voltage range on the ADC input is restricted goes low to indicate that data is ready to be read from the to a range between GND + 100 mV and VDD – 100 mV. Care AD7783’s data register. It is reset high when a read operation must be taken in setting up the common-mode voltage and input from the data register is complete. It also goes high prior to voltage range so that these limits are not exceeded; otherwise, the updating of the output register to indicate when not to there will be a degradation in linearity and noise performance. read from the device to ensure that a data read is not attempted
Programmable Gain Amplifier
while the register is being updated. The digital conversion is The output from the buffer on the ADC is applied to the input of also output on this pin. the on-chip programmable gain amplifier (PGA). The PGA gain CS is used to select the device and to place the device in standby range is programmed via the RANGE pin. With an external 2.5 V mode. When CS is taken low, the AD7783 is powered up, the reference applied, the PGA can be programmed to have a bipolar PLL locks, and the device initiates a conversion. The device will range of ± 160 mV (RANGE = 0) or ± 2.56 V (RANGE = 1). continue to convert until CS is taken high. When CS is taken These are the ranges that should appear at the input to the high, the AD7783 is placed in standby mode, minimizing the on-chip PGA. current consumption. The conversion is aborted, DOUT and
Bipolar Configuration/Output Coding
SCLK are three-stated, and the result in the data register is lost. The analog input on the AD7783 accepts bipolar input voltage Figure 2 shows the timing diagram for interfacing to the AD7783 ranges. Signals on the AIN(+) input of the ADC are referenced with CS used to decode the part. –8– REV. C Document Outline FEATURES INTERFACE POWER ON-CHIP FUNCTIONS APPLICATIONS FUNCTIONAL BLOCK DIAGRAM BASIC CONNECTION DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics ADC CIRCUIT INFORMATION Overview NOISE PERFORMANCE DIGITAL INTERFACE MASTER MODE (MODE = 0) SLAVE MODE (MODE = 1) CIRCUIT DESCRIPTION Analog Input Channel Programmable Gain Amplifier Bipolar Configuration/Output Coding Excitation Currents Crystal Oscillator Reference Input Grounding and Layout OUTLINE DIMENSIONS Revision History