Datasheet AD7671 (Analog Devices) - 5

AD7671 TIMING SPECIFICATIONS (continued) Parameter Symbol Min Typ Max Unit
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 0.75/1/1.25 ms (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay t11 20 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 5 15 ns Refer to Figures 17 and 18 (Master Serial Interface Modes)2 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay (Read during Convert) t17 25/275/525 ns (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay3 t18 4 ns Internal SCLK Period3 t19 25 40 ns Internal SCLK HIGH3 t20 15 ns Internal SCLK LOW3 t21 9.5 ns SDOUT Valid Setup Time3 t22 4.5 ns SDOUT Valid Hold Time3 t23 2 ns SCLK Last Edge to SYNC Delay3 t24 3 CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read after Convert3 t28 See Table II ms CNVST LOW to SYNC Asserted Delay t29 0.75/1/1.25 ms (Warp Mode/Normal Mode/Impulse Mode) Master Serial Read after Convert SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figures 19 and 21 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 16 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode. Specifications subject to change without notice.
Table II. Serial Clock Timings in Master Read after Convert DIVSCLK[1] 0 0 1 1 DIVSCLK[0] 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 4 20 20 20 ns Internal SCLK Period Minimum t19 25 50 100 200 ns Internal SCLK Period Maximum t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 15 25 50 100 ns Internal SCLK LOW Minimum t21 9 24 49 99 ns SDOUT Valid Setup Time Minimum t22 4.5 22 22 22 ns SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns BUSY HIGH Width Maximum (Warp) t28 1.5 2 3 5.25 ms BUSY HIGH Width Maximum (Normal) t28 1.75 2.25 3.25 5.5 ms BUSY HIGH Width Maximum (Impulse) t28 2 2.5 3.5 5.75 ms Specifications subject to change without notice. REV. C –4– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PulSAR Selection PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTION DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Bipolar Zero Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Voltage Reference Input Scaler Reference Input (Bipolar Input Ranges) Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE SLAVE SERIAL INTERFACE External Clock MASTER SERIAL INTERFACE Internal Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7671 Performance OUTLINE DIMENSIONS Revision History