Datasheet AD7671 (Analog Devices) - 9

制造商Analog Devices
描述16-Bit, 1 MSPS CMOS ADC
页数 / 页25 / 9 — AD7671. DEFINITION OF SPECIFICATIONS. Effective Number of Bits (ENOB). …
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AD7671. DEFINITION OF SPECIFICATIONS. Effective Number of Bits (ENOB). Integral Nonlinearity Error (INL)

AD7671 DEFINITION OF SPECIFICATIONS Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL)

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AD7671 DEFINITION OF SPECIFICATIONS Effective Number of Bits (ENOB) Integral Nonlinearity Error (INL)
A measurement of the resolution with a sine wave input. It is Linearity error refers to the deviation of each individual code related to S/(N+D) by the following formula: from a line drawn from “negative full scale” through “positive ENOB = (S/[N + D]dB – 1.76)/6.02) full scale.” The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a and is expressed in bits. level 1 1/2 LSB beyond the last code transition. The deviation is
Total Harmonic Distortion (THD)
measured from the middle of each code to the true straight line. The rms sum of the first five harmonic components to the rms
Differential Nonlinearity Error (DNL)
value of a full-scale input signal, expressed in decibels. In an ideal ADC, code transitions are 1 LSB apart. Differential
Signal-to-Noise Ratio (SNR)
nonlinearity is the maximum deviation from this ideal value. It is The ratio of the rms value of the actual input signal to the rms often specified in terms of resolution for which no missing codes sum of all other spectral components below the Nyquist fre- are guaranteed. quency, excluding harmonics and dc. The value for SNR is
Full-Scale Error
expressed in decibels. The last transition (from 011 . 10 to 011 . 11 in twos
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
complement coding) should occur for an analog voltage 1 1/2 LSB The ratio of the rms value of the actual input signal to the rms below the nominal full scale (2.499886 V for the ±2.5 V range). sum of all other spectral components below the Nyquist fre- The full-scale error is the deviation of the actual level of the last quency, including harmonics but excluding dc. The value for transition from the ideal level. S/(N+D) is expressed in decibels.
Bipolar Zero Error Aperture Delay
The difference between the ideal midscale input voltage (0 V) and A measure of the acquisition performance measured from the the actual voltage producing the midscale output code. falling edge of the CNVST input to when the input signal is
Unipolar Zero Error
held for a conversion. In Unipolar Mode, the first transition should occur at a level
Transient Response
1/2 LSB above analog ground. The unipolar zero error is the The time required for the AD7671 to achieve its rated accuracy deviation of the actual transition from that point. after a full-scale step function is applied to its input.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. REV. C –8– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PulSAR Selection PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTION DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Bipolar Zero Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Voltage Reference Input Scaler Reference Input (Bipolar Input Ranges) Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE SLAVE SERIAL INTERFACE External Clock MASTER SERIAL INTERFACE Internal Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7671 Performance OUTLINE DIMENSIONS Revision History