Datasheet AD7492 (Analog Devices) - 6

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AD7492 Parameter A Version2 B Version2 Unit Test Conditions/Comments
DC ACCURACY fS = 1 MSPS for AD7492 fS = 400 kSPS for AD7492-4 Resolution 12 12 Bits Integral Nonlinearity ±1.5 LSB max ±0.6 LSB typ VDD = 5 V ±1 LSB max VDD = 3 V Differential Nonlinearity +1.5/−0.9 +1.5/−0.9 LSB max Guaranteed no missed codes to 12 bits (A and B versions) Offset Error ±9 ±9 LSB max Gain Error ±2.5 ±2.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to 2.5 0 to 2.5 V DC Leakage Current ±1 ±1 μA max Input Capacitance 33 33 pF typ REFERENCE OUTPUT REF OUT Output Voltage Range 2.5 2.5 V ±1.5% for specified performance LOGIC INPUTS Input High Voltage, V 4 INH VDRIVE × 0.7 VDRIVE × 0.7 V min VDD = 5 V ± 5% Input Low Voltage, V 4 INL VDRIVE × 0.3 VDRIVE × 0.3 V max VDD = 5 V ± 5% Input Current, IIN ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Capacitance, C 3, 5 IN 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 VDRIVE − 0.2 V min ISOURCE = 200 μA Output Low Voltage, VOL 0.4 0.4 V max ISINK = 200 μA Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Straight (Natural) Binary Binary CONVERSION RATE Conversion Time 880 880 ns max Track/Hold Acquisition Time 120 120 ns min Throughput Rate 1 1 MSPS max Conversion time + acquisition time for AD7492 400 kSPS max Conversion time + acquisition time for AD7492-4 POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or DVDD. Normal Mode 3 3 mA max fS = 1 MSPS, typ 2.2 mA fS = 400 kSPS, Typ 2.2 mA (AD7492-4) Quiescent Current 1.8 1.8 mA max Partial Sleep Mode 250 250 μA max Static, typ 190 μA Full Sleep Mode 1 1 μA max Static, typ 200 nA Power Dissipation4, 6 Digital I/Ps = 0 V or DVDD Normal Mode 15 15 mW max VDD = 5 V Partial Sleep Mode 1.25 1.25 mW max VDD = 5 V Full Sleep Mode 5 5 μW max VDD = 5 V 1 Only A version specification applies to the AD7492-4. 2 Temperature ranges as follows: A and B versions: −40°C to +85°C. 3 500 kHz sine wave specifications do not apply for the AD7492-4. 4 VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE. 5 Sample tested @ 25°C to ensure compliance. 6 See the Power vs. Throughput section. Rev. A | Page 5 of 24 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7492-5 AD7492/AD7492-4 TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PEFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME DC ACQUISITION TIME ANALOG INPUT PARALLEL INTERFACE OPERATING MODES POWER-UP GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING OUTLINE DIMENSIONS ORDERING GUIDE