Datasheet AD73360L (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Six-Input Channel Analog Front End |
| 页数 / 页 | 33 / 5 — AD73360L. S/(N+D) – dB. 100. IOL. TO OUTPUT. 2.1V. PIN. –10. –85. –75. … |
| 文件格式/大小 | PDF / 304 Kb |
| 文件语言 | 英语 |
AD73360L. S/(N+D) – dB. 100. IOL. TO OUTPUT. 2.1V. PIN. –10. –85. –75. –65. –55. –45. –35. –25. –15. 15pF. 3.17. IN –. dBm0. IOH. MCLK. t13. SCLK*
该数据表的模型线
文件文字版本
AD73360L t1 80 t2 70 60 50 t3 40
Figure 1. MCLK Timing
30 S/(N+D) – dB 20 100
A IOL 10 0 TO OUTPUT 2.1V PIN C –10 L –85 –75 –65 –55 –45 –35 –25 –15 –5 5 15pF V 3.17 IN – dBm0 100
A IOH
Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) Figure 2. Load Circuit for Timing Specifications
t t2 t 1 3 MCLK t13 SCLK* t5 t6 t4 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I) THREE- STATE SCLK (O) t7 SDIFS (I) t8 t8 t7 SDI (I) D15 D14 D1 D0 D15 t9 t THREE- 10 SDOFS (O) STATE t THREE- t 11 12 STATE SDO (O) D15 D2 D1 D0 D15 D14
Figure 4. Serial Port (SPORT) –4– REV. 0
Figure 1. MCLK Timing
30 S/(N+D) – dB 20 100
A IOL 10 0 TO OUTPUT 2.1V PIN C –10 L –85 –75 –65 –55 –45 –35 –25 –15 –5 5 15pF V 3.17 IN – dBm0 100
A IOH
Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) Figure 2. Load Circuit for Timing Specifications
t t2 t 1 3 MCLK t13 SCLK* t5 t6 t4 * SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I) THREE- STATE SCLK (O) t7 SDIFS (I) t8 t8 t7 SDI (I) D15 D14 D1 D0 D15 t9 t THREE- 10 SDOFS (O) STATE t THREE- t 11 12 STATE SDO (O) D15 D2 D1 D0 D15 D14
Figure 4. Serial Port (SPORT) –4– REV. 0