Datasheet AD73360L (Analog Devices) - 10

AD73360L
Figure 7 shows the various stages of filtering that are employed
Decimation Filter
in a typical AD73360L application. In Figure 7a we see the trans- The digital filter used in the AD73360L carries out two impor- fer function of the external analog antialias filter. Even though it tant functions. Firstly, it removes the out-of-band quantization is a single RC pole, its cutoff frequency is sufficiently far away noise, which is shaped by the analog modulator and secondly, it from the initial sampling frequency (DMCLK/8) that it takes care decimates the high-frequency bitstream to a lower rate 15-bit word. of any signals that could be aliased by the sampling frequency. The antialiasing decimation filter is a sinc-cubed digital filter This also shows the major difference between the initial oversam- that reduces the sampling rate from DMCLK/8 to DMCLK/ pling rate and the bandwidth of interest. In Figure 7b, the signal 256, and increases the resolution from a single bit to 15 bits. Its and noise-shaping responses of the sigma-delta modulator are Z transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a mini- shown. The signal response provides further rejection of any mal group delay of 25 µs. high-frequency signals while the noise-shaping will push the inherent quantization noise to an out-of-band position. The detail Word growth in the decimator is determined by the sampling of Figure 7c shows the response of the digital decimation filter rate. At 64 kHz sampling, where the oversampling ratio between (sinc-cubed response) with nulls every multiple of DMCLK/ the sigma-delta modulator and decimator output equals 32, 256, which is the decimation filter update rate. The final detail there are five bits per stage of the three-stage Sinc3 filter. Due to in Figure 7d shows the application of a final antialias filter in the symmetry within the sigma-delta modulator, the LSB will always DSP engine. This has the advantage of being implemented accord- be a zero; therefore, the 16-bit ADC output word will have ing to the user’s requirements and available MIPS. The filtering in 2 LSBs equal to zero, one due to the sigma-delta symmetry and Figures 7a through 7c is implemented in the AD73360L. the other being a padded zero to make up a 16-bit word. At lower sampling rates, decimator word growth will be greater than the 16-bit sample word, therefore truncation occurs in trans- ferring the decimator output as the ADC word. For example at 8 kHz sampling, word growth reaches 24 bits due to the OSR of 256 between sigma-delta modulator and decimator. This yields eight bits per stage of the three stage Sinc3 filter.
ADC Coding F
The ADC coding scheme is in two’s complement format (see
B = 4kHz FSINIT = DMCLK/8
Figure 8). The output words are formed by the decimation a. Analog Antialias Filter Transfer Function filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the final
SIGNAL TRANSFER FUNCTION
output of the ADC block. In 16-bit Data Mode this value is left shifted with the LSB being set to 0. For input values equal to or greater than positive full scale, however, the output word is set
NOISE TRANSFER FUNCTION
at 0x7FFF, which has the LSB set to 1. In mixed Control/Data Mode, the resolution is fixed at 15 bits, with the MSB of the 16-bit transfer being used as a flag bit to indicate either control
FB = 4kHz FSINIT = DMCLK/8
or data in the frame. b. Analog Sigma-Delta Modulator Transfer Function
VREF + (VREF
ⴛ
0.32875) VINN ANALOG VREF INPUT V V REF – (VREF
ⴛ
0.32875) INP F 10...00 00...00 01...11 B = 4kHz FSINTER = DMCLK/256 ADC CODE DIFFERENTIAL
c. Digital Decimator Transfer Function
VREF + (VREF
ⴛ
0.6575) VINN ANALOG INPUT V V INP REF – (VREF
ⴛ
0.6575) FB = 4kHz F F SFINAL = 8kHz SINTER = DMCLK/256 10...00 00...00 01...11
d. Final Filter LPF (HPF) Transfer Function
ADC CODE SINGLE-ENDED
Figure 7. DC Frequency Responses Figure 8. ADC Transfer Function REV. 0 –9–