Datasheet AD7470, AD7472 (Analog Devices) - 10

AD7470/AD7472 CIRCUIT DESCRIPTION TYPICAL CONNECTION DIAGRAM CONVERTER OPERATION
Figure 5 shows a typical connection diagram for the AD7470/ The AD7470/AD7472 are 10-bit/12-bit successive approxima- AD7472. Conversion is initiated by a falling edge on CONVST. tion analog-to-digital converters based around a capacitive Once CONVST goes low, the BUSY signal goes high, and at DAC. The AD7470/AD7472 can convert analog input signals in the end of conversion, the falling edge of BUSY is used to acti- the range 0 V to VREF. Figure 2 shows a very simplified sche- vate an interrupt service routine. The CS and RD lines are then matic of the ADC. The control logic, SAR, and the capacitive activated in parallel to read the 10- or 12-data bits. The recom- DAC are used to add and subtract fixed amounts of charge mended REF IN voltage is 2.5 V providing an analog input from the sampling capacitor to bring the comparator back into a range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar balanced condition. ADC. It is recommended to perform a dummy conversion after power-up as the first conversion result could be incorrect. This
COMPARATOR
also ensures that the part is in the correct mode of operation. The CONVST pin should not be floating when power is applied
CAPACITIVE DAC
as a rising edge on CONVST might not wake up the part. In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic output voltage values being either 0 V or DV
V
DD. The voltage
IN SWITCHES
applied to V
V
DRIVE controls the voltage value of the output logic
REF
signals. For example, if DVDD is supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic output voltage levels would be
SAR
either 0 V or 3 V. This feature allows the AD7470/AD7472 to interface to 3 V parts while still enabling the ADC to process
CONTROL CONTROL LOGIC
signals at 5 V supply.
INPUTS OUTPUT DATA 10-/12-BIT PARALLEL ANALOG SUPPLY
Figure 2. Simplified Block Diagram of AD7470/AD7472
+ + 10
␮
F 0.1
␮
F 47
␮
F 2.7V–5.25V
Figure 3 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a
AV V DD DRIVE
balanced condition and the sampling capacitor acquires the
DVDD 1nF
signal on V
AD7470/
IN. ␮
C/
␮
P AD7472 2.5V* REF IN 0.1
␮
F 10
␮
F 0V TO VIN CAPACITIVE REF IN DAC PARALLED DB0– INTERFACE DB9 (DB11) 2k A
⍀
CS VIN CONVST SW1 B CONTROL LOGIC RD SW2 BUSY COMPARATOR AGND *RECOMMENDED REF IN VOLTAGE
Figure 3. ADC Acquisition Phase Figure 5. Typical Connection Diagram Figure 4 shows the ADC during conversion. When conversion starts, SW2 will open and SW1 will move to position B, causing the comparator to become unbalanced. The ADC then runs through its successive approximation routine and brings the comparator back into a balanced condition. When the compara- tor is rebalanced, the conversion result is available in the SAR register.
CAPACITIVE DAC 2k A
⍀
VIN SW1 B CONTROL LOGIC SW2 COMPARATOR AGND
Figure 4. ADC Conversion Phase –10– REV. B Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track-and-Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Aperture Delay Aperture Jitter CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME Reference Input DC ACQUISITION TIME ANALOG INPUT CLOCK SOURCES PARALLEL INTERFACE OPERATING MODES Mode 1 (High Speed Sampling) Mode 2 (Sleep Mode) Burst Mode VDRIVE POWER-UP Power vs. Throughput Mode 1 Mode 2 Typical Performance Characteristics GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING AD7470/AD7472 to ADSP-2185 Interface AD7470/AD7472 to ADSP-21065 Interface AD7470/AD7472 to TMS320C25 Interface AD7470/AD7472 to PIC17C4x Interface AD7470/AD7472 to 80C186 Interface OUTLINE DIMENSIONS Revision History