Datasheet AD73360 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 6-Channel AFE Processor for General Purpose Applications Including Industrial Power Metering or Multi-Channel Analog Inputs |
| 页数 / 页 | 36 / 7 — AD73360. (AVDD = 3 V. 10%; DVDD = 3 V. 10%; AGND = DGND = 0 V; T. TIMING … |
| 修订版 | B |
| 文件格式/大小 | PDF / 381 Kb |
| 文件语言 | 英语 |
AD73360. (AVDD = 3 V. 10%; DVDD = 3 V. 10%; AGND = DGND = 0 V; T. TIMING CHARACTERISTICS. A = TMlN to TMAX, unless otherwise
该数据表的模型线
文件文字版本
AD73360 (AVDD = 3 V
ⴞ
10%; DVDD = 3 V
ⴞ
10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +85
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK
(AVDD = 5 V
ⴞ
10%; DVDD = 5 V
ⴞ
10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +85
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK –6– REV. B
ⴞ
10%; DVDD = 3 V
ⴞ
10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +85
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK
(AVDD = 5 V
ⴞ
10%; DVDD = 5 V
ⴞ
10%; AGND = DGND = 0 V; T TIMING CHARACTERISTICS A = TMlN to TMAX, unless otherwise noted) Limit at Parameter TA = –40
ⴗ
C to +85
ⴗ
C Unit Description
Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK –6– REV. B