link to page 15 link to page 15 AD9288PIN CONFIGURATION AND FUNCTION DESCRIPTIONS) BA(MSCAAAAAAAADDDVENVGNDD7D6D5D4D3D2D1D048 47 46 45 44 43 42 41 40 39 38 37GND 136 NCPIN 1AINA 2IDENTIFIER35 NCAINA 334 GNDDFS 433 VDDREFINA 532 GNDREFAD9288OUT631 VDREFTOP VIEWINB 730 VD(Not to Scale)S1 829 GNDS2 928 VDDAINB 1027 GNDA11INB26 NCGND 1225 NC13 14 15 16 17 18 19 20 21 22 23 24DBBBBBBBBBVCDDV GNDD6D5D4D3D2D1D0NC = NO CONNECTEN) D7 B 00585-002 (MS Figure 5. Pin Configuration Table 3. Pin No.NameDescription 1, 12, 16, 27, 29, GND Ground 32, 34, 45 2 AINA Analog Input for Channel A. 3 AINA Analog Input for Channel A (Complementary). 4 DFS Data Format Select. Offset binary output available if set low. Twos complement output available if set high. 5 REFINA Reference Voltage Input for Channel A. 6 REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S1 User Select 1. Refer to Table 4. Tied with respect to VD. 9 S2 User Select 2. Refer to Table 4. Tied with respect to VD. 10 AINB Analog Input for Channel B (Complementary). 11 AINB Analog Input for Channel B. 13, 30, 31, 48 VD Analog Supply (3 V). 14 ENCB Clock Input for Channel B. 15, 28, 33, 46 VDD Digital Supply (3 V). 17–24 D7B–D0 B Digital Output for Channel B. 25, 26, 35, 36 NC Do Not Connect. 37–44 D0A–D7 A Digital Output for Channel A. 47 ENC A Clock Input for Channel A. Rev. C | Page 8 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS EXPLANATION OF TEST LEVELS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION USING THE AD9288 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER-SELECTABLE OPTIONS AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE