Datasheet AD7887 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP |
| 页数 / 页 | 25 / 6 — Data Sheet. AD7887. TIMING SPECIFICATIONS1. Table 2. Limit at TMIN, TMAX. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 470 Kb |
| 文件语言 | 英语 |
Data Sheet. AD7887. TIMING SPECIFICATIONS1. Table 2. Limit at TMIN, TMAX. (A, B Versions). Parameter. 4.75 V to 5.25 V. 2.7 V to 3.6 V
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Data Sheet AD7887 TIMING SPECIFICATIONS1 Table 2. Limit at TMIN, TMAX (A, B Versions) Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description
f 2 SCLK 2 2 MHz max tCONVERT 14.5 × tSCLK 14.5 × tSCLK tACQ 1.5 × tSCLK 1.5 × tSCLK Throughput time = tCONVERT + tACQ = 16 tSCLK t1 10 10 ns min CS to SCLK setup time t 3 2 30 60 ns max Delay from CS until DOUT three-state disabled t 3 3 75 100 ns max Data access time after SCLK falling edge t4 20 20 ns min Data setup time prior to SCLK rising edge t5 20 20 ns min Data valid to SCLK hold time t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t 4 8 80 80 ns max CS rising edge to DOUT high impedance t9 5 5 μs typ Power-up time from shutdown 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
002
200µA IOH
06191- Figure 2. Load Circuit for Digital Output Timing Specifications Rev. E | Page 5 of 24 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications Timing Specifications6F Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Control Register Theory of Operation Circuit Information Converter Operation ADC Transfer Function Typical Connection Diagram Analog Input On-Chip Reference Power-Down Options Power-Up Times Power vs. Throughput Rate Modes of Operation Mode 1 (PM1 = 0, PM0 = 0) Mode 2 (PM1 = 0, PM0 = 1) Mode 3 (PM1 = 1, PM0 = 0) Mode 4 (PM1 = 1, PM0 = 1) Serial Interface Microprocessor Interfacing AD7887 to TMS320C5x AD7887 to ADSP-21xx AD7887 to DSP56xxx AD7887 to MC68HC11 AD7887 to 8051 AD7887 to PIC16C6x/PIC16C7x Application Hints Grounding and Layout Outline Dimensions Ordering Guide Automotive Products
Data Sheet AD7887 TIMING SPECIFICATIONS1 Table 2. Limit at TMIN, TMAX (A, B Versions) Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description
f 2 SCLK 2 2 MHz max tCONVERT 14.5 × tSCLK 14.5 × tSCLK tACQ 1.5 × tSCLK 1.5 × tSCLK Throughput time = tCONVERT + tACQ = 16 tSCLK t1 10 10 ns min CS to SCLK setup time t 3 2 30 60 ns max Delay from CS until DOUT three-state disabled t 3 3 75 100 ns max Data access time after SCLK falling edge t4 20 20 ns min Data setup time prior to SCLK rising edge t5 20 20 ns min Data valid to SCLK hold time t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t 4 8 80 80 ns max CS rising edge to DOUT high impedance t9 5 5 μs typ Power-up time from shutdown 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
002
200µA IOH
06191- Figure 2. Load Circuit for Digital Output Timing Specifications Rev. E | Page 5 of 24 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications Timing Specifications6F Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Control Register Theory of Operation Circuit Information Converter Operation ADC Transfer Function Typical Connection Diagram Analog Input On-Chip Reference Power-Down Options Power-Up Times Power vs. Throughput Rate Modes of Operation Mode 1 (PM1 = 0, PM0 = 0) Mode 2 (PM1 = 0, PM0 = 1) Mode 3 (PM1 = 1, PM0 = 0) Mode 4 (PM1 = 1, PM0 = 1) Serial Interface Microprocessor Interfacing AD7887 to TMS320C5x AD7887 to ADSP-21xx AD7887 to DSP56xxx AD7887 to MC68HC11 AD7887 to 8051 AD7887 to PIC16C6x/PIC16C7x Application Hints Grounding and Layout Outline Dimensions Ordering Guide Automotive Products