Datasheet AD7729 (Analog Devices) - 10

制造商Analog Devices
描述3 V, Dual Sigma-Delta ADC with Auxiliary DAC
页数 / 页17 / 10 — AD7729. FUNCTIONAL DESCRIPTION. BASEBAND CODEC Receive Section. 4.7k. …
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AD7729. FUNCTIONAL DESCRIPTION. BASEBAND CODEC Receive Section. 4.7k. IRxP. IRx. I CHANNEL. IRxN. 100pF. QRxP. Q CHANNEL. QRx. QRxN

AD7729 FUNCTIONAL DESCRIPTION BASEBAND CODEC Receive Section 4.7k IRxP IRx I CHANNEL IRxN 100pF QRxP Q CHANNEL QRx QRxN

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AD7729 FUNCTIONAL DESCRIPTION AD7729 BASEBAND CODEC Receive Section 4.7k
V The receive section consists of I and Q receive channels, each
IRxP
comprising of a simple switched-capacitor filter followed by a
IRx I CHANNEL
15-bit sigma-delta ADC. On-board digital filters, which form
4.7k
V
IRxN
part of the sigma-delta ADCs, also perform critical system-level
100pF 100pF
filtering. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. The receive sec- tion is also provided with a low power sleep mode to place the
4.7k
V
QRxP
receive section on standby between receive bursts, drawing only
Q CHANNEL QRx
minimal current.
QRxN 4.7k
V
Switched Capacitor Input
The receive section analog front-end is sampled at 13 MHz by a
100pF 100pF
switched-capacitor filter. The filter has a zero at 6.5 MHz as
REFOUT
shown in Figure 8a. The receive channel also contains a digital
TO INPUT BIAS
low-pass filter (further details are contained in the following
CIRCUITRY
section) which operates at a clock frequency of 6.5 MHz. Due
0.1
m
F REFCAP VOLTAGE
to the sampling nature of the digital filter, the passband is re-
REFERENCE 0.1
m
F
peated about the operating clock frequency and at multiples of the clock frequency (Figure 8b). Because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs Figure 9. Example Circuit for Differential Input (Figure 8c), further simplifying the external antialiasing require- Figure 10 shows the recommended single-ended analog input ments (see Figures 9 and 10). circuit.
0 dBs AD7729 FRONT-END ANALOG FILTER TRANSFER 4.7k
V
IRxP FUNCTION MHz IRx 6.5 13 19.5 I CHANNEL 100pF
a) Switched-Cap Filter Frequency Response
IRxN 0 dBs 4.7k
V
QRxP QRx Q CHANNEL DIGITAL FILTER 100pF TRANSFER MHz FUNCTION QRxN 6.5 13 19.5
b) Digital Filter Frequency Response
V REFOUT BIAS HIGH SPEED 0 dBs BUFFER SYSTEM FILTER 0.1
m
F REFCAP VOLTAGE TRANSFER REFERENCE MHz FUNCTION 0.1
m
F 6.5 13 19.5
c) Overall System Response of the Receive Channel Figure 10. Example Circuit for Single-Ended Input Figure 8. The circuitry of Figure 9 implements first-order low-pass filters with a 3 dB point at 338 kHz; these are the only filters that must be implemented external to the baseband section to pre- vent aliasing of the sampled signal. REV. 0 –9–