Datasheet AD7894 (Analog Devices) - 4

AD7894 Parameter A Versionsl B Versions1 Units Test Conditions/Comments
POWER REQUIREMENTS VDD +5 +5 V nom ±5% for Specified Performance IDD 5.5 5.5 mA max Digital Inputs @ VDD, VDD = 5 V ± 5% Power Dissipation 27.5 27.5 mW max Typically 20 mW Power-Down Mode IDD @ TMIN to TMAX 20 20 µA max Digital Inputs @ GND, VDD = 5 V ± 5% Power Dissipation TMIN to TMAX 100 100 µW max Typ 15 µW NOTES 1Temperature ranges are as follows: A, B Versions: –40°C to +85°C. 2Applies to Mode 1 operation. See Operating Modes section. 3See Terminology. 4Sample tested @ +25°C to ensure compliance. 5This 10 µs includes the “wake-up” time from standby. This “wake-up” time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of CONVST, for narrow CONVST pulsewidth the conversion time is effectively the “wake-up” time plus conversion time, hence 10 µs. This can be seen from Figure 3. Note that if the CONVST pulsewidth is greater than 5 µs, the effective conversion time will increase beyond 10 µs. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 (VDD = +5 V
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5%, GND = 0 V, REF IN = +2.5 V) Parameter A, B Versions Units Test Conditions/Comments
t1 40 ns min CONVST Pulsewidth t2 31.252 ns min SCLK High Pulsewidth t3 31.252 ns min SCLK Low Pulsewidth t4 603 ns max Data Access Time after Falling Edge of SCLK VDD = 5 V ± 5% t5 10 ns min Data Hold Time after Falling Edge of SCLK t6 204 ns max Bus Relinquish Time after Falling Edge of SCLK NOTES 1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2The SCLK maximum frequency is 16 MHz. Care must be taken when interfacing to account for the data access time, t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK frequency with which the user’s system can operate. See Serial Interface section for more information. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Junction Temperature . +150°C (T SOIC Package, Power Dissipation . 450 mW A = +25°C unless otherwise noted) V ␣ ␣ θ DD to GND . –0.3␣ V to +7 V JA Thermal Impedance . 170°C/W Analog Input Voltage to GND ␣ ␣ Lead Temperature, Soldering ␣ ␣ AD7894-10 . ± 17 V ␣ ␣ ␣ ␣ Vapor Phase (60 sec) . +215°C ␣ ␣ AD7894-3 . ± 7 V ␣ ␣ ␣ ␣ Infrared (15 sec) . +220°C ␣ ␣ AD7894-2 . –5 V to +10 V *Stresses above those listed under Absolute Maximum Ratings may cause perma- Reference Input Voltage to GND . –0.3 V to VDD + 0.3 V nent damage to the device. This is a stress rating only; functional operation of the Digital Input Voltage to GND . –0.3 V to V device at these or any other conditions above those listed in the operational DD + 0.3 V Digital Output Voltage to GND . –0.3 V to V sections of this specification is not implied. Exposure to absolute maximum rating DD + 0.3 V conditions for extended periods may affect device reliability. Operating Temperature Range ␣ ␣ Commercial (A, B Versions) . –40°C to +85°C ␣ ␣ Storage Temperature Range . –65°C to +150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although the AD7894 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3–