Datasheet AD7894 (Analog Devices) - 9

AD7894 CONVST BUSY 250ns MIN SCLK tCONVERT = 10
m
s PART CONVERSION CONVERSION SERIAL READ READ OPERATION OUTPUT WAKES IS INITIATED; ENDS OPERATION SHOULD END 250ns SERIAL SHIFT UP TRACK/HOLD 10
m
s LATER PRIOR TO NEXT REGISTER GOES INTO RISING EDGE OF IS RESET HOLD CONVST
Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function is Initiated
t2 = t3 = 31.25ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 20ns MAX @ 5V, A, B, VERSIONS t2 t3 SCLK (I/P) 1 2 3 4 15 16 t6 t t5 4 THREE- THREE-STATE 2 LEADING STATE DOUT (O/P) ZEROS DB13 DB12 DB0
Figure 5. Data Read Operation
Mode 2 Operation (Auto Sleep After Conversion)
easy-to-use interface to most microcontrollers, DSP processors The timing diagram in Figure 4 is for optimum performance in and shift registers. operating Mode 2, where the part automatically goes into sleep Figure 5 shows the timing diagram for the read operation to the mode once BUSY goes low, after conversion and “wakes up” AD7894. The serial clock input (SCLK) provides the clock before the next conversion takes place. This is achieved by keep- source for the serial interface. Serial data is clocked out from ing CONVST low at the end of conversion, whereas it was high the SDATA line on the falling edge of this clock and is valid on at the end of conversion for Mode 1 Operation. The rising edge both the rising and falling edges of SCLK. The advantage of of CONVST “wakes up” the AD7894. This wake-up time is having the data valid on both the rising and falling edges of the typically 5 µs and is controlled internally by a monostable cir- SCLK is to give the user greater flexibility in interfacing to the cuit. While the AD7894 is waking up there is some digital activ- part and so a wider range of microprocessor and microcontrol- ity internal to the part. If the falling edge of CONVST (putting ler interfaces can be accommodated. This also explains the two the track/hold amplifier into hold mode) should occur during timing figures, t4 and t5, that are quoted on the diagram. The this digital activity, noise will be injected into the track/hold time t4 specifies how long after the falling edge of the SCLK the amplifier resulting in a poor conversion. For optimum results next data bit becomes valid, whereas the time t5 specifies for the CONVST pulse should be between 40 ns and 2 µs or greater how long after the falling edge of the SCLK the current data bit than 6 µs in width. The narrower pulse will allow a system to is valid. The first leading zero is clocked out on the first rising instruct the AD7894 to begin waking up and perform a conver- edge of SCLK. Note that the first zero will be valid on the first sion when ready, whereas the pulse greater than 6 µs will give falling edge of SCLK even though the data access time is speci- control over when the sampling instant takes place. Note that fied at 60 ns for the other bits. The reason for this is that the the 10 µs wake-up time shown in Figure 4 is for a CONVST pulse first bit will be clocked out faster than the other bits is due to less than 2 µs. If a CONVST pulse greater than 6 µs is used, the the internal architecture of the part. Sixteen clock pulses must conversion will not complete for a further 5 µs after the falling edge be provided to the part to access to full conversion result. The of CONVST. Even though the part is in sleep mode, data can still AD7894 provides two leading zeros followed by the 14-bit be read from it. The read operation consists of 16 clock cycles as in conversion result starting with the MSB (DB13). The last data Mode 1 Operation. For the fastest serial clock of 16 MHz, the read bit to be clocked out on the penultimate falling clock edge is the operation will take 1.0 µs and this must be complete at least 250 ns LSB (DB0). On the 16th falling edge of SCLK the LSB (DB0) before the falling edge of the next CONVST, to allow the track/ will be valid for a specified time to allow the bit to be read on hold amplifier to have enough time to settle. This mode is very the falling edge of the SCLK and then the SDATA line is dis- useful when the part is converting at a slow rate, as the power abled (three-stated). After this last bit has been clocked out, consumption will be significantly reduced from that of Mode 1 the SCLK input should return low and remain low until the Operation. next serial data read operation. If there are extra clock pulses
Serial Interface
after the 16th clock, the AD7894 will start over again with The serial interface to the AD7894 consists of just three wires, a outputting data from its output register and the data bus will serial clock input (SCLK) and the serial data output (SDATA) no longer be three-stated even when the clock stops. Provided and a conversion status output (BUSY). This allows for an the serial clock has stopped before the next falling edge of –8– REV. 0