Datasheet AD7817, AD7818 (Analog Devices) - 6

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AD7817/AD7818 Data Sheet TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted. Sample tested during initial release and after any redesign or process changes that may affect the parameters. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. See Figure 17, Figure 18, Figure 21, and Figure 22.
Table 2. Parameter A Version/B Version Unit Test Conditions/Comments
tPOWER-UP 2 μs max Power-up time from rising edge of CONVST t1a 9 μs max Conversion time Channel 1 to Channel 4 t1b 27 μs max Conversion time temperature sensor t2 20 ns min CONVST pulse width t3 50 ns max CONVST falling edge to BUSY rising edge t4 0 ns min CS falling edge to RD/WR falling edge setup time t5 0 ns min RD/WR falling edge to SCLK falling edge setup t6 10 ns min DIN setup time before SCLK rising edge t7 10 ns min DIN hold time after SCLK rising edge t8 40 ns min SCLK low pulse width t9 40 ns min SCLK high pulse width t10 0 ns min CS falling edge to RD/WR rising edge setup time t11 0 ns min RD/WR rising edge to SCLK falling edge setup time t 1 12 20 ns max DOUT access time after RD/WR rising edge t 1 13 20 ns max DOUT access time after SCLK falling edge t 1, 2 14a 30 ns max DOUT bus relinquish time after falling edge of RD/WR t 1, 2 14b 30 ns max DOUT bus relinquish time after rising edge of CS t15 150 ns max BUSY falling edge to OTI falling edge t16 40 ns min RD/WR rising edge to OTI rising edge t17 400 ns min SCLK rising edge to CONVST falling edge (acquisition time of T/H) 1 These figures are measured with the load circuit of Figure 3. They are defined as the time required for DOUT to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and 0.4 V or 2 V for VDD = 3 V ± 10%, as shown in Table 1. 2 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of the external bus loading capacitances.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
3
200µA I
-00
OL
16 013 Figure 3. Load Circuit for Access Time and Bus Relinquish Time Rev. E | Page 6 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY CONTROL BYTE Address Register Overtemperature Register CIRCUIT INFORMATION CONVERTER DETAILS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Analog Input DC Acquisition Time AC Acquisition Time ON-CHIP REFERENCE ADC TRANSFER FUNCTION TEMPERATURE MEASUREMENT TEMPERATURE MEASUREMENT ERROR DUE TO REFERENCE ERROR SELF-HEATING CONSIDERATIONS OPERATING MODES Mode 1 Mode 2 POWER vs. THROUGHPUT AD7817 SERIAL INTERFACE Read Operation Write Operation Simplifying the Serial Interface AD7818 SERIAL INTERFACE MODE Read Operation Write Operation OUTLINE DIMENSIONS ORDERING GUIDE