Datasheet AD9283 (Analog Devices) - 9

AD9283 Digital Outputs 2.0
The digital outputs are TTL/CMOS compatible. The output
1.5
buffers are powered from a separate supply, allowing adjustment of the output voltage swing to ease interfacing with 2.5 V or
1.0
3.3 V logic. The AD9283 goes into a low power state within two clock cycles following the assertion of the PWRDWN input.
0.5
PWRDWN is asserted with a logic high. During power-down
B 0.0 LS
the outputs transition to a high impedance state. The time it takes to achieve optimal performance after disabling the power-
–0.5
down mode is approximately 15 clock cycles. Care should be
–1.0
taken when loading the digital outputs of any high speed ADC. Large output loads create current transients on the chip that can
–1.5
degrade the converter’s performance.
–2.0 Voltage Reference CODE
A stable and accurate 1.25 V voltage reference is built into the TPC 13. Integral Nonlinearity AD9283 (VREF OUT). In normal operation, the internal refer- ence is used by strapping Pins 2 and 3 of the AD9283 together. The input range can be adjusted by varying the reference volt-
APPLICATIONS
age applied to the AD9283. No degradation in performance
Theory of Operation
occurs when the reference is adjusted ± 5%. The full-scale range The analog signal is applied differentially or single-endedly to of the ADC tracks reference voltage changes linearly. Whether the inputs of the AD9283. The signal is buffered and fed for- used or not, the internal reference (Pin 2) should be bypassed ward to an on-chip sample-and-hold circuit. The ADC core with a 0.1 µF capacitor to ground. architecture is a bit-per-stage pipeline type converter utilizing switch capacitor techniques. The bit-per-stage blocks determine
Timing
the 5 MSBs and drive a FLASH converter to encode the 3 LSBs. The AD9283 provides latched data outputs with four pipeline Each of the 5 MSB stages provides sufficient overlap and error delays. Data outputs are available one propagation delay (tPD) correction to allow optimization of performance with respect to after the rising edge of the encode command (Figure 1. Timing comparator accuracy. The output staging block aligns the data, Diagram). The minimum guaranteed conversion rate to the carries out the error correction and feeds the data to the eight ADC is 1 MSPS. The dynamic performance of the converter output buffers. The AD9283 includes an on-chip reference will degrade at encode rates below this sample rate. (nominally 1.25 V) and generates all clocking signals from one
Evaluation Board
externally applied encode command. This makes the ADC easy The AD9283 evaluation board offers an easy way to test the to interface with and requires very few external components for AD9283. It only requires a 3 V supply, an analog input and operation. encode clock to test the AD9283. The board is shipped with the
ENCODE Input
100 MSPS grade ADC. The ENCODE input is fully TTL/CMOS compatible with a The analog input to the board accepts a 1 V p-p signal centered nominal threshold of 1.5 V. Care was taken on the chip to at ground. J1 should be used (Jump E3–E4, E18–E19) to drive match clock line delays and maintain sharp clock logic transi- the ADC through Transformer T1. J2 should be used for single- tions. Any high speed A/D converter is extremely sensitive to ended input drive (Jump E19–E21). the quality of the sampling clock provided by the user. This Both J1 and J2 are terminated to 50 Ω on the PCB. Each analog ADC uses an on-chip sample-and-hold circuit which is essen- path is ac-coupled to an on-chip resistor divider which provides tially a mixer. Any timing jitter on the ENCODE will be com- the required dc bias. bined with the desired signal and degrade the high frequency performance of the ADC. The user is advised to give commen- A (TTL/CMOS Level) sample clock is applied to connector surate thought to the clock source. J3 which is terminated through 50 Ω on the PCB. This clock is buffered by U5 which also provides the clocks for the 574
Analog Input
latches, DAC, and the off-card latch clock CLKCON. (Timing The analog input to the ADC is fully differential and both inputs can be modified at E17.) are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. For peak performance There is a reconstruction DAC (AD9760) on the PCB. The the inputs are biased at 0.3 × V DAC is on the board to assist in debug only—the outputs D. See the specification table for allowable common-mode range when dc coupling the input. should not be used to measure performance of the ADC. The inputs are also buffered to reduce the load the user needs to drive. For best dynamic performance, the impedances at AIN and AIN should be matched. The importance of this increases with sampling rate and analog input frequency. The nominal input range is 1.024 V p-p. –8– REV. C