Datasheet AD9224 (Analog Devices) - 3

制造商Analog Devices
描述12-Bit 40 MSPS Monolithic A/D Converter
页数 / 页24 / 3
修订版A
文件格式/大小PDF / 316 Kb
文件语言英语

Datasheet AD9224 Analog Devices, 修订版: A 页 3

该数据表的模型线

文件文字版本

AD9224 AC SPECIFICATIONS (AVDD = +5 V, DRVDD = +3 V, f SAMPLE = 40 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted) Parameter
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
fINPUT = 2.5 MHz
fINPUT = 10 MHz
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.5 MHz
fINPUT = 10 MHz Min Typ 65
63.5 68.3
68.0 dB
dB 65.3
64.6 69.1
68.4 dB
dB TOTAL HARMONIC DISTORTION (THD)
fINPUT = 2.5 MHz
fINPUT = 10 MHz Max –80
–78 SPURIOUS FREE DYNAMIC RANGE
fINPUT = 2.5 MHz
fINPUT = 10 MHz
Full Power Bandwidth
Small Signal Bandwidth
Aperture Delay
Aperture Jitter 71.1
67.9 –71
–67.4 81
79
120
120
1
4 Units dB
dB
dB
dB
MHz
MHz
ns
ps rms Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVDD = +5 V, DRVDD = +5 V, unless otherwise noted)
Parameters
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = DRVDD)
Low Level Input Current (VIN = 0 V)
Input Capacitance
LOGIC OUTPUTS (With DRVDD = 5 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA)
Output Capacitance
LOGIC OUTPUTS (With DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA) Symbol Min VIH
VIL
IIH
IIL
CIN +3.5 VOH
VOH
VOL
VOL
COUT +4.5
+2.4 VOH
VOH
VOL
VOL +2.95
+2.80 Typ Max Units +1.0
+10
+10
5 V
V
µA
µA
pF 5 V
V
V
V
pF –10
–10 +0.4
+0.1 +0.4
+0.05 V
V
V
V Specifications subject to change without notice. SWITCHING SPECIFICATIONS (T MIN to TMAX with AVDD = + 5 V, DRVDD = +5 V, CL = 20 pF) Parameters Symbol Min Clock Period1
CLOCK Pulsewidth High2
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay (Latency) tC
tCH
tCL
tOD 25
12.37
12.37
13
3 NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
2
For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text.
Specifications subject to change without notice. REV. A Typ –3– Max Units
ns
ns
ns
ns
Clock Cycles