Datasheet AD7723 (Analog Devices) - 8

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AD7723 t5 t4 t2 2.3V CLKIN 0.8V t3 t1 t7 t6 FSI t8 t9 SCO t9 t10
01186-003 Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output
32 CLKIN CYCLES CLKIN t8 FSI (SFMT = 1) t14 SCO (CFMT = 0) t11 FSO (SFMT = 0) t t11 12 FSO (SFMT = 1) t13
004
SDO D15 D14 D13 D2 D1 D0 D15 D14
01186- Figure 4. Serial Mode 1: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)
32 CLKIN CYCLES CLKIN t8 FSI t14 SCO (CFMT = 0) t11 t12 FSO t13 SDO D2 D1 D0 D15 D14 D13 D12 D11 D5 D4 D3 D2 D1 D0 D15 D14
01186-005 Figure 5. Serial Mode 2: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) Rev. C | Page 7 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT DRIVING THE ANALOG INPUTS APPLYING THE REFERENCE CLOCK GENERATION SYSTEM SYNCHRONIZATION DATA INTERFACING PARALLEL INTERFACE SERIAL INTERFACE TWO-CHANNEL MULTIPLEXED OPERATION SERIAL INTERFACE TO DSPs AD7723 TO ADSP-21xx INTERFACE AD7723 TO SHARC INTERFACE AD7723 TO DSP56002 INTERFACE AD7723 TO TMS320C5x INTERFACE GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE