AD7723t18CLKINtt1919t17DRDYt20DB0–DB15WORD N – 1WORD NWORD N + 1 01186-008 Figure 8. Parallel Mode Read Timing, CS and RD Tied Logic Low CLKINt18t19DRDYtt2219RD/CSt 21t22t21t24DB0–DB15VALID DATA 01186-009 t23 Figure 9. Parallel Mode Read Timing, CS = RD t28CLKINt26SYNCt25DRDYt 01186-010 27 Figure 10. SYNC Timing Rev. C | Page 9 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION APPLYING THE AD7723 ANALOG INPUT RANGE ANALOG INPUT DRIVING THE ANALOG INPUTS APPLYING THE REFERENCE CLOCK GENERATION SYSTEM SYNCHRONIZATION DATA INTERFACING PARALLEL INTERFACE SERIAL INTERFACE TWO-CHANNEL MULTIPLEXED OPERATION SERIAL INTERFACE TO DSPs AD7723 TO ADSP-21xx INTERFACE AD7723 TO SHARC INTERFACE AD7723 TO DSP56002 INTERFACE AD7723 TO TMS320C5x INTERFACE GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE