Datasheet AD7705, AD7706 (Analog Devices) - 8

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AD7705/AD7706 TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V; GND = 0 V; fCLKIN = 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.
Table 2. Timing Characteristics
1
,
2
Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments
f 3, 4 CLKIN 400 kHz min Master clock frequency (crystal oscillator or externally supplied) 2.5 MHz max For specified performance tCLKIN LO 0.4 × tCLKIN ns min Master clock input low time, tCLKIN = 1/fCLKIN tCLKIN HI 0.4 × tCLKIN ns min Master clock input high time t1 500 × tCLKIN ns nom DRDY high time t2 100 ns min RESET pulse width Read Operation t3 0 ns min DRDY to CS setup time t4 120 ns min CS falling edge to SCLK rising edge setup time t 5 5 0 ns min SCLK falling edge to data valid delay 80 ns max VDD = 5 V 100 ns max VDD = 3.0 V t6 100 ns min SCLK high pulse width t7 100 ns min SCLK low pulse width t8 0 ns min CS rising edge to SCLK rising edge hold time t 6 9 10 ns min Bus relinquish time after SCLK rising edge 60 ns max VDD = 5 V 100 ns max VDD = 3.0 V t10 100 ns max SCLK falling edge to DRDY high7 Write Operation t11 120 ns min CS falling edge to SCLK rising edge setup time t12 30 ns min Data valid to SCLK rising edge setup time t13 20 ns min Data valid to SCLK rising edge hold time t14 100 ns min SCLK high pulse width t15 100 ns min SCLK low pulse width t16 0 ns min CS rising edge to SCLK rising edge hold time 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 19 and Figure 20. 3 The fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw higher current than specified, and possibly become uncalibrated. 4 The AD7705/AD7706 are production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). They are guaranteed by characterization to operate at 400 kHz. 5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high upon completion of the first read from the device after an output update. The same data can be reread while DRDY is high, but care should be taken that subsequent reads do not occur close to the next output update.
ISINK (800
μ
A AT VDD = 5V 100
μ
A AT VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200
μ
A AT VDD = 5V 100mA AT VDD = 3V)
01166-002 Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. C | Page 8 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTPUT NOISE (5 V OPERATION) OUTPUT NOISE (3 V OPERATION) TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATION REGISTER (RS2, RS1, RS0 = 0, 0, 0) SETUP REGISTER (RS2, RS1, RS0 = 0, 0, 1); POWER-ON/RESET STATUS: 01 HEXADECIMAL CLOCK REGISTER (RS2, RS1, RS0 = 0, 1, 0); POWER-ON/RESET STATUS: 05 HEXADECIMAL DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1) TEST REGISTER (RS2, RS1, RS0 = 1, 0, 0); POWER-ON/RESET STATUS: 00 HEXADECIMAL ZERO-SCALE CALIBRATION REGISTER (RS2, RS1, RS0 = 1, 1, 0); POWER-ON/RESET STATUS: 1F4000 HEXADECIMAL FULL-SCALE CALIBRATION REGISTER (RS2, RS1, RS0 = 1, 1, 1); POWER-ON/RESET STATUS: 5761AB HEXADECIMAL Calibration Sequences CIRCUIT DESCRIPTION ANALOG INPUT Ranges Sample Rate BIPOLAR/UNIPOLAR INPUT REFERENCE INPUT DIGITAL FILTERING Filter Characteristics Postfiltering ANALOG FILTERING CALIBRATION Self-Calibration System Calibration Span and Offset Limits Power-Up and Calibration THEORY OF OPERATION CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE DIGITAL INTERFACE CONFIGURING THE AD7705/AD7706 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7705/AD7706-to-68HC11 Interface AD7705/AD7706-to-8051 Interface AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface CODE FOR SETTING UP THE AD7705/AD7706 C Code for Interfacing AD7705 to 68HC11 APPLICATIONS PRESSURE MEASUREMENT TEMPERATURE MEASUREMENT SMART TRANSMITTERS BATTERY MONITORING OUTLINE DIMENSIONS ORDERING GUIDE